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vc/intel/fsp/mtl: Add Psi[1-3]Threshold UPDs to FSP-M header file 

Export Power State Current 1, 2 and 3 Threshold configuration entries.

BUG=b:308002192

Change-Id: Iff4467720541efbdedace12431cd1f6f66fca8e6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Jeremy Compostella 2023-10-18 12:39:10 -07:00 committed by Matt DeVillier
parent 648ed149a1
commit e68650a656
1 changed files with 23 additions and 2 deletions
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25
src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
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@ -1442,9 +1442,30 @@ typedef struct {
**/
UINT16 DcLoadline[6];
/** Offset 0x063C - Reserved
/** Offset 0x063C - Power State 1 Threshold current
PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range
0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA,
[3] through [5] are Reserved.
**/
UINT8 Reserved34[90];
UINT16 Psi1Threshold[6];
/** Offset 0x0648 - Power State 2 Threshold current
PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range
0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA,
[3] through [5] are Reserved.
**/
UINT16 Psi2Threshold[6];
/** Offset 0x0654 - Power State 3 Threshold current
PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range
0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA,
[3] through [5] are Reserved.
**/
UINT16 Psi3Threshold[6];
/** Offset 0x0660 - Reserved
**/
UINT8 Reserved34[54];
/** Offset 0x0696 - Thermal Design Current enable/disable
Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,