google/cyan: convert to variant configuration
Setup cyan to be the baseboard for other Google Braswell boards, to be added in subsequent commits: - Keep code common to all Google Braswell boards in the baseboard, and separate out the board-specific bits into the new cyan variant. - Define the I2C ACPI devices such that they can be easily reused for other variants. - Switch the trackpad/touchscreen interrupts from edge to level, for better performance/compatibility, as was done with all previous Google boards. - Add code to the baseboard to allow optional variant-specific parameters to be used for both memory and silicon init. - Remove superfluous includes, replace some hardcoded values with variables, and correct typos/formatting errors. Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
parent
982688a41a
commit
e69a9c7581
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@ -1,7 +1,5 @@
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if BOARD_GOOGLE_CYAN
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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config BOARD_GOOGLE_BASEBOARD_CYAN
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def_bool n
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select BOARD_ROMSIZE_KB_8192
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_MEC
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@ -14,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS
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select SOC_INTEL_BRASWELL
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select HAVE_ACPI_RESUME
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if BOARD_GOOGLE_BASEBOARD_CYAN
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select VBOOT_LID_SWITCH
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@ -33,14 +33,22 @@ config MAINBOARD_DIR
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string
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default google/cyan
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config VARIANT_DIR
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string
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default "cyan" if BOARD_GOOGLE_CYAN
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config MAINBOARD_PART_NUMBER
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string
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default "Cyan"
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default "Cyan" if BOARD_GOOGLE_CYAN
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config MAINBOARD_VENDOR
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string
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default "Google"
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config DEVICETREE
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string
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default "variants/cyan/devicetree.cb" if BOARD_GOOGLE_CYAN
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config VGA_BIOS_FILE
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string
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depends on VGA_BIOS
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@ -61,5 +69,6 @@ config VGA_BIOS_ID
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config GBB_HWID
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string
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depends on CHROMEOS
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default "CYAN TEST A-A 1829"
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endif # BOARD_GOOGLE_CYAN
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default "CYAN TEST A-A 1829" if BOARD_GOOGLE_CYAN
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endif # BOARD_GOOGLE_BASEBOARD_CYAN
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@ -1,2 +1,3 @@
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config BOARD_GOOGLE_CYAN
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bool "Cyan"
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select BOARD_GOOGLE_BASEBOARD_CYAN
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@ -14,17 +14,18 @@
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## GNU General Public License for more details.
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##
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subdirs-y += spd
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romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
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romstage-y += spd/spd.c
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ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c
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ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c
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ramstage-y += boardid.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += ec.c
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ramstage-y += irqroute.c
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ramstage-y += ramstage.c
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ramstage-y += w25q64.c
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ramstage-y += boardid.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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@ -0,0 +1,117 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Scope (\_SB.PCI0.I2C2)
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{
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/* Maxim Audio Codec */
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Device (MAXM) /* Audio Codec driver I2C */
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{
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Name (_ADR, 0)
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Name (_HID, AUDIO_CODEC_HID)
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Name (_CID, AUDIO_CODEC_CID)
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Name (_DDN, AUDIO_CODEC_DDN)
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Name (_UID, 1)
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/* Add DT style bindings with _DSD */
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Name (_DSD, Package () {
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ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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/* set maxim micbias to 2.8v */
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Package () { "maxim,micbias", 3 },
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}
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})
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Method(_CRS, 0x0, NotSerialized)
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{
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Name(SBUF,ResourceTemplate ()
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{
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I2CSerialBus(
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AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */
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ControllerInitiated, /* SlaveMode: default to ControllerInitiated */
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400000, /* ConnectionSpeed: in Hz */
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AddressingMode7Bit, /* Addressing Mode: default to 7 bit */
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"\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */
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)
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GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
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"\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX }
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} )
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Return (SBUF)
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}
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Method (_STA)
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{
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If (LEqual (\S2EN, 1)) {
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Return (0xF)
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} Else {
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Return (0x0)
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}
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}
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}
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Device (TISW) /* TI Switch driver I2C */
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{
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Name (_ADR, 0)
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Name (_HID, TI_SWITCH_HID)
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Name (_CID, TI_SWITCH_CID)
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Name (_DDN, TI_SWITCH_DDN)
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Name (_UID, 1)
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/* Add DT style bindings with _DSD */
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Name (_DSD, Package () {
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ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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/* set ti micbias to 2.8v */
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Package () { "ti,micbias", 7 },
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}
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})
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Method(_CRS, 0x0, NotSerialized)
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{
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Name(SBUF,ResourceTemplate ()
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{
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I2CSerialBus(
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TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */
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ControllerInitiated, /* SlaveMode: default to ControllerInitiated */
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400000, /* ConnectionSpeed: in Hz */
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AddressingMode7Bit, /* Addressing Mode: default to 7 bit */
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"\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */
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)
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GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
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"\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX }
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} )
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Return (SBUF)
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}
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Method (_STA)
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{
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Return (0xF)
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}
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}
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}
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Scope (\_SB.PCI0.LPEA)
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{
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Name (GBUF, ResourceTemplate ()
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{
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/* Jack Detect (index 0) */
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GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
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"\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX }
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})
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}
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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* Copyright (C) 2105 Intel Corp.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -14,63 +14,8 @@
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* GNU General Public License for more details.
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*/
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#define DPTF_TSR0_SENSOR_ID 0
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#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
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#define DPTF_TSR0_PASSIVE 49
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#define DPTF_TSR0_CRITICAL 75
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/* Include Variant DPTF */
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#include <variant/acpi/dptf.asl>
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#define DPTF_TSR1_SENSOR_ID 1
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#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
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#define DPTF_TSR1_PASSIVE 65
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#define DPTF_TSR1_CRITICAL 85
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#define DPTF_TSR2_SENSOR_ID 2
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#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
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#define DPTF_TSR2_PASSIVE 49
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#define DPTF_TSR2_CRITICAL 75
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#define DPTF_ENABLE_CHARGER
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/* Charger performance states, board-specific values from charger and EC */
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Name (CHPS, Package () {
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Package () { 0, 0, 0, 0, 255, 0x400, "mA", 0 }, /* 1.0A (MAX) */
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Package () { 0, 0, 0, 0, 12, 0x300, "mA", 0 }, /* 0.77A */
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Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
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Package () { 0, 0, 0, 0, 4, 0x100, "mA", 0 }, /* 0.25A */
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Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
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})
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/* Mainboard specific _PDL is 1GHz */
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Name (MPDL, 8)
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 0 */
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Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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{
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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2000, /* PowerLimitMinimum */
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6200, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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200 /* StepSize */
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},
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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8000, /* PowerLimitMinimum */
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8000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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1000 /* StepSize */
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}
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})
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/* Include DPTF */
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/* Include SoC DPTF */
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#include <acpi/dptf/dptf.asl>
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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* Copyright (C) 2105 Intel Corp.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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|
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@ -15,7 +15,7 @@
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* GNU General Public License for more details.
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*/
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#include <onboard.h>
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#include <variant/onboard.h>
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Scope (\_SB)
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{
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@ -26,189 +26,6 @@ Scope (\_SB)
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}
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}
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Scope (\_SB.PCI0.I2C1)
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{
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Device (ETSA)
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{
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Name (_HID, "ELAN0001")
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Name (_DDN, "Elan Touchscreen ")
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Name (_UID, 5)
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Name (ISTP, 0) /* TouchScreen */
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Method(_CRS, 0x0, NotSerialized)
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{
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Name(BUF0,ResourceTemplate ()
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{
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I2CSerialBus(
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0x10, /* SlaveAddress */
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ControllerInitiated, /* SlaveMode */
|
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400000, /* ConnectionSpeed */
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AddressingMode7Bit, /* AddressingMode */
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"\\_SB.PCI0.I2C1", /* ResourceSource */
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)
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Interrupt (ResourceConsumer, Edge, ActiveLow)
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{
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BOARD_TOUCH_IRQ
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}
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} )
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Return (BUF0)
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}
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Method (_STA)
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{
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If (LEqual (\S1EN, 1)) {
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Return (0xF)
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} Else {
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Return (0x0)
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}
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}
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Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
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|
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/* Allow device to power off in S0 */
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Name (_S0W, 4)
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}
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}
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Scope (\_SB.PCI0.I2C2)
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||||
{
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/* Maxim Audio Codec */
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Device (MAXM) /* Audio Codec driver I2C */
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{
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Name (_ADR, 0)
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Name (_HID, AUDIO_CODEC_HID)
|
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Name (_CID, AUDIO_CODEC_CID)
|
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Name (_DDN, AUDIO_CODEC_DDN)
|
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Name (_UID, 1)
|
||||
|
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/* Add DT style bindings with _DSD */
|
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Name (_DSD, Package () {
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ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
|
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/* set maxim micbias to 2.8v */
|
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Package () { "maxim,micbias", 3 },
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}
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})
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|
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Method(_CRS, 0x0, NotSerialized)
|
||||
{
|
||||
Name(SBUF,ResourceTemplate ()
|
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{
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I2CSerialBus(
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AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */
|
||||
ControllerInitiated, /* SlaveMode: default to ControllerInitiated */
|
||||
400000, /* ConnectionSpeed: in Hz */
|
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AddressingMode7Bit, /* Addressing Mode: default to 7 bit */
|
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"\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */
|
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)
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GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
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"\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX }
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} )
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Return (SBUF)
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}
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|
||||
Method (_STA)
|
||||
{
|
||||
If (LEqual (\S2EN, 1)) {
|
||||
Return (0xF)
|
||||
} Else {
|
||||
Return (0x0)
|
||||
}
|
||||
}
|
||||
}
|
||||
Device (TISW) /* TI Switch driver I2C */
|
||||
{
|
||||
Name (_ADR, 0)
|
||||
Name (_HID, TI_SWITCH_HID)
|
||||
Name (_CID, TI_SWITCH_CID)
|
||||
Name (_DDN, TI_SWITCH_DDN)
|
||||
Name (_UID, 1)
|
||||
|
||||
/* Add DT style bindings with _DSD */
|
||||
Name (_DSD, Package () {
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package () {
|
||||
/* set ti micbias to 2.8v */
|
||||
Package () { "ti,micbias", 7 },
|
||||
}
|
||||
})
|
||||
|
||||
Method(_CRS, 0x0, NotSerialized)
|
||||
{
|
||||
Name(SBUF,ResourceTemplate ()
|
||||
{
|
||||
I2CSerialBus(
|
||||
TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */
|
||||
ControllerInitiated, /* SlaveMode: default to ControllerInitiated */
|
||||
400000, /* ConnectionSpeed: in Hz */
|
||||
AddressingMode7Bit, /* Addressing Mode: default to 7 bit */
|
||||
"\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */
|
||||
)
|
||||
|
||||
GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
|
||||
"\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX }
|
||||
|
||||
} )
|
||||
Return (SBUF)
|
||||
}
|
||||
|
||||
Method (_STA)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_SB.PCI0.I2C6)
|
||||
{
|
||||
Device (ETPA)
|
||||
{
|
||||
Name (_HID, "ELAN0000")
|
||||
Name (_DDN, "Elan Touchpad")
|
||||
Name (_UID, 3)
|
||||
Name (ISTP, 1) /* Touchpad */
|
||||
|
||||
Name (_CRS, ResourceTemplate()
|
||||
{
|
||||
I2cSerialBus (
|
||||
0x15, /* SlaveAddress */
|
||||
ControllerInitiated, /* SlaveMode */
|
||||
400000, /* ConnectionSpeed */
|
||||
AddressingMode7Bit, /* AddressingMode */
|
||||
"\\_SB.PCI0.I2C6", /* ResourceSource */
|
||||
)
|
||||
GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
|
||||
"\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX }
|
||||
})
|
||||
|
||||
Method (_STA)
|
||||
{
|
||||
If (LEqual (\S6EN, 1)) {
|
||||
Return (0xF)
|
||||
} Else {
|
||||
Return (0x0)
|
||||
}
|
||||
}
|
||||
|
||||
Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
|
||||
|
||||
/* Allow device to power off in S0 */
|
||||
Name (_S0W, 4)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_SB.PCI0.LPEA)
|
||||
{
|
||||
Name (GBUF, ResourceTemplate ()
|
||||
{
|
||||
/* Jack Detect (index 0) */
|
||||
GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
|
||||
"\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX }
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_SB.GPNC)
|
||||
{
|
||||
Method (_AEI, 0, NotSerialized) // _AEI: ACPI Event Interrupts
|
||||
|
@ -225,3 +42,6 @@ Scope (\_SB.GPNC)
|
|||
{
|
||||
}
|
||||
}
|
||||
|
||||
/* Variant-specific I2C devices */
|
||||
#include <variant/acpi/mainboard.asl>
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
|
||||
/* mainboard configuration */
|
||||
#include <ec.h>
|
||||
#include <onboard.h>
|
||||
#include <variant/onboard.h>
|
||||
|
||||
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
|
||||
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
|
||||
|
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
Scope (\_SB.PCI0.I2C1)
|
||||
{
|
||||
Device (ETSA)
|
||||
{
|
||||
Name (_HID, "ELAN0001")
|
||||
Name (_DDN, "Elan Touchscreen ")
|
||||
Name (_UID, 5)
|
||||
Name (ISTP, 0) /* TouchScreen */
|
||||
|
||||
Method(_CRS, 0x0, NotSerialized)
|
||||
{
|
||||
Name(BUF0,ResourceTemplate ()
|
||||
{
|
||||
I2CSerialBus(
|
||||
0x10, /* SlaveAddress */
|
||||
ControllerInitiated, /* SlaveMode */
|
||||
400000, /* ConnectionSpeed */
|
||||
AddressingMode7Bit, /* AddressingMode */
|
||||
"\\_SB.PCI0.I2C1", /* ResourceSource */
|
||||
)
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow)
|
||||
{
|
||||
BOARD_TOUCH_IRQ
|
||||
}
|
||||
|
||||
} )
|
||||
Return (BUF0)
|
||||
}
|
||||
|
||||
Method (_STA)
|
||||
{
|
||||
If (LEqual (\S1EN, 1)) {
|
||||
Return (0xF)
|
||||
} Else {
|
||||
Return (0x0)
|
||||
}
|
||||
}
|
||||
|
||||
Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
|
||||
|
||||
/* Allow device to power off in S0 */
|
||||
Name (_S0W, 4)
|
||||
}
|
||||
}
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
Scope (\_SB.PCI0.I2C6)
|
||||
{
|
||||
Device (ETPA)
|
||||
{
|
||||
Name (_HID, "ELAN0000")
|
||||
Name (_DDN, "Elan Touchpad")
|
||||
Name (_UID, 3)
|
||||
Name (ISTP, 1) /* Touchpad */
|
||||
|
||||
Name (_CRS, ResourceTemplate()
|
||||
{
|
||||
I2cSerialBus (
|
||||
0x15, /* SlaveAddress */
|
||||
ControllerInitiated, /* SlaveMode */
|
||||
400000, /* ConnectionSpeed */
|
||||
AddressingMode7Bit, /* AddressingMode */
|
||||
"\\_SB.PCI0.I2C6", /* ResourceSource */
|
||||
)
|
||||
GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,,
|
||||
"\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX }
|
||||
})
|
||||
|
||||
Method (_STA)
|
||||
{
|
||||
If (LEqual (\S6EN, 1)) {
|
||||
Return (0xF)
|
||||
} Else {
|
||||
Return (0x0)
|
||||
}
|
||||
}
|
||||
|
||||
Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
|
||||
|
||||
/* Allow device to power off in S0 */
|
||||
Name (_S0W, 4)
|
||||
}
|
||||
}
|
|
@ -15,19 +15,9 @@
|
|||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/acpigen.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <cbmem.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <soc/acpi.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/nvs.h>
|
||||
#include <string.h>
|
||||
#include <types.h>
|
||||
|
||||
void acpi_create_gnvs(global_nvs_t *gnvs)
|
||||
{
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
Vendor name: Google
|
||||
Board name: Cyan Braswell reference board
|
||||
Board name: Cyan Braswell baseboard
|
||||
Category: laptop
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright(C) 2013 Google Inc.
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
|
@ -16,7 +16,7 @@
|
|||
|
||||
#include <boardid.h>
|
||||
#include <stdlib.h>
|
||||
#include "ec/google/chromeec/ec.h"
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
|
||||
uint8_t board_id(void)
|
||||
{
|
||||
|
|
|
@ -15,9 +15,7 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <bootstate.h>
|
||||
#include <device/device.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
#include "ec.h"
|
||||
|
||||
|
|
|
@ -14,9 +14,8 @@
|
|||
*/
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include <boardid.h>
|
||||
#include "onboard.h"
|
||||
|
||||
__attribute__ ((weak))
|
||||
void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
|
||||
{
|
||||
}
|
||||
|
|
|
@ -14,13 +14,7 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <cbfs.h>
|
||||
#include <console/console.h>
|
||||
#include <lib.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <string.h>
|
||||
|
||||
/* All FSP specific code goes in this block */
|
||||
void mainboard_romstage_entry(struct romstage_params *rp)
|
||||
|
@ -33,6 +27,7 @@ void mainboard_romstage_entry(struct romstage_params *rp)
|
|||
romstage_common(rp);
|
||||
}
|
||||
|
||||
__attribute__ ((weak))
|
||||
void mainboard_memory_init_params(struct romstage_params *params,
|
||||
MEMORY_INIT_UPD *memory_params)
|
||||
{
|
||||
|
|
|
@ -25,7 +25,7 @@
|
|||
#include <soc/pm.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#include "onboard.h"
|
||||
#include <variant/onboard.h>
|
||||
|
||||
/* The wake gpio is SUS_GPIO[0]. */
|
||||
#define WAKE_GPIO_EN SUS_GPIO_EN0
|
||||
|
|
|
@ -26,24 +26,10 @@
|
|||
#include <soc/romstage.h>
|
||||
#include <string.h>
|
||||
#include <spd_bin.h>
|
||||
#include "spd_util.h"
|
||||
|
||||
/*
|
||||
* 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
|
||||
* 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz
|
||||
* 0b0010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
|
||||
* 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz
|
||||
* 0b0100 - 4GiB total - 2 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz
|
||||
* 0b0101 - 4GiB total - 2 x 2GiB Micro MT41K256M16TW-107 1600MHz
|
||||
* 0b0110 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz
|
||||
* 0b0111 - 2GiB total - 1 x 2GiB Micro MT41K256M16TW-107 1600MHz
|
||||
*/
|
||||
static const uint32_t dual_channel_config = (1 << 0) | (1 << 1)
|
||||
| (1 << 4) | (1 << 5);
|
||||
|
||||
static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
|
||||
__attribute__ ((weak)) uint8_t get_ramid(void)
|
||||
{
|
||||
int ram_id = 0;
|
||||
|
||||
gpio_t spd_gpios[] = {
|
||||
GP_SW_80, /* SATA_GP3, RAMID0 */
|
||||
GP_SW_67, /* I2C3_SCL, RAMID1 */
|
||||
|
@ -51,45 +37,24 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
|
|||
GP_SW_64, /* I2C3_SDA, RAMID3 */
|
||||
};
|
||||
|
||||
ram_id = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
|
||||
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
|
||||
}
|
||||
|
||||
static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
|
||||
{
|
||||
int ram_id = 0;
|
||||
int spd_index = 0;
|
||||
|
||||
ram_id = get_ramid();
|
||||
printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
|
||||
if (ram_id >= total_spds)
|
||||
|
||||
spd_index = get_variant_spd_index(ram_id, dual);
|
||||
if (spd_index >= total_spds) {
|
||||
printk(BIOS_ERR, "SPD index > total SPDs\n");
|
||||
return NULL;
|
||||
|
||||
/* Determine if this is a single or dual channel memory system */
|
||||
if (dual_channel_config & (1 << ram_id))
|
||||
*dual = 1;
|
||||
|
||||
/* Display the RAM type */
|
||||
switch (ram_id) {
|
||||
case 0:
|
||||
printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646Q-HYK0 1600MHz\n");
|
||||
break;
|
||||
case 2:
|
||||
printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646Q-HYK0 1600MHz\n");
|
||||
break;
|
||||
case 1:
|
||||
printk(BIOS_DEBUG, "4GiB Hynix H5TC4G63CFR-PBA 1600MHz\n");
|
||||
break;
|
||||
case 3:
|
||||
printk(BIOS_DEBUG, "2GiB Hynix H5TC4G63CFR-PBA 1600MHz\n");
|
||||
break;
|
||||
case 4:
|
||||
printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646E-BYK0 1600MHz\n");
|
||||
break;
|
||||
case 5:
|
||||
printk(BIOS_DEBUG, "4GiB Micro MT41K256M16TW-107 1600MHz\n");
|
||||
break;
|
||||
case 6:
|
||||
printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646E-BYK0 1600MHz\n");
|
||||
break;
|
||||
case 7:
|
||||
printk(BIOS_DEBUG, "2GiB Micro MT41K256M16TW-107 1600MHz\n");
|
||||
break;
|
||||
}
|
||||
|
||||
/* Return the serial product data for the RAM */
|
||||
return &spd_file_content[SPD_PAGE_LEN * ram_id];
|
||||
return &spd_file_content[SPD_PAGE_LEN * spd_index];
|
||||
}
|
||||
|
||||
/* Copy SPD data for on-board memory */
|
||||
|
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Matt DeVillier
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef SPD_UTIL_H
|
||||
#define SPD_UTIL_H
|
||||
|
||||
uint8_t get_ramid(void);
|
||||
int get_variant_spd_index(int ram_id, int *dual);
|
||||
|
||||
#endif /* SPD_UTIL_H */
|
|
@ -14,7 +14,9 @@
|
|||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
romstage-y += spd.c
|
||||
romstage-y += spd_util.c
|
||||
|
||||
ramstage-y += gpio.c
|
||||
|
||||
SPD_BIN = $(obj)/spd.bin
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
Vendor name: Google
|
||||
Board name: Cyan
|
||||
Category: laptop
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
|
@ -14,7 +14,7 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "irqroute.h"
|
||||
#include <mainboard/google/cyan/irqroute.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <stdlib.h>
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define DPTF_TSR0_SENSOR_ID 0
|
||||
#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
|
||||
#define DPTF_TSR0_PASSIVE 49
|
||||
#define DPTF_TSR0_CRITICAL 75
|
||||
|
||||
#define DPTF_TSR1_SENSOR_ID 1
|
||||
#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
|
||||
#define DPTF_TSR1_PASSIVE 65
|
||||
#define DPTF_TSR1_CRITICAL 85
|
||||
|
||||
#define DPTF_TSR2_SENSOR_ID 2
|
||||
#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
|
||||
#define DPTF_TSR2_PASSIVE 49
|
||||
#define DPTF_TSR2_CRITICAL 75
|
||||
|
||||
#define DPTF_ENABLE_CHARGER
|
||||
|
||||
/* Charger performance states, board-specific values from charger and EC */
|
||||
Name (CHPS, Package () {
|
||||
Package () { 0, 0, 0, 0, 255, 0x400, "mA", 0 }, /* 1.0A (MAX) */
|
||||
Package () { 0, 0, 0, 0, 12, 0x300, "mA", 0 }, /* 0.77A */
|
||||
Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
|
||||
Package () { 0, 0, 0, 0, 4, 0x100, "mA", 0 }, /* 0.25A */
|
||||
Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
|
||||
})
|
||||
|
||||
/* Mainboard specific _PDL is 1GHz */
|
||||
Name (MPDL, 8)
|
||||
|
||||
Name (DTRT, Package () {
|
||||
/* CPU Throttle Effect on CPU */
|
||||
Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Effect on Temp Sensor 0 */
|
||||
Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },
|
||||
})
|
||||
|
||||
Name (MPPC, Package ()
|
||||
{
|
||||
0x2, /* Revision */
|
||||
Package () { /* Power Limit 1 */
|
||||
0, /* PowerLimitIndex, 0 for Power Limit 1 */
|
||||
2000, /* PowerLimitMinimum */
|
||||
6200, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
200 /* StepSize */
|
||||
},
|
||||
Package () { /* Power Limit 2 */
|
||||
1, /* PowerLimitIndex, 1 for Power Limit 2 */
|
||||
8000, /* PowerLimitMinimum */
|
||||
8000, /* PowerLimitMaximum */
|
||||
1000, /* TimeWindowMinimum */
|
||||
1000, /* TimeWindowMaximum */
|
||||
1000 /* StepSize */
|
||||
}
|
||||
})
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Matt DeVillier
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* Elan touchscreen */
|
||||
#include <acpi/touchscreen_elan.asl>
|
||||
|
||||
/* Elan trackpad */
|
||||
#include <acpi/trackpad_elan.asl>
|
||||
|
||||
/* Maxim audio codec */
|
||||
#include <acpi/codec_maxim.asl>
|
|
@ -17,7 +17,7 @@
|
|||
#ifndef ONBOARD_H
|
||||
#define ONBOARD_H
|
||||
|
||||
#include "irqroute.h"
|
||||
#include <mainboard/google/cyan/irqroute.h>
|
||||
|
||||
/*
|
||||
* Calculation of gpio based irq.
|
||||
|
@ -53,7 +53,7 @@
|
|||
#define BOARD_TOUCHSCREEN_NAME "touchscreen"
|
||||
#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2)
|
||||
#define BOARD_TOUCHSCREEN_I2C_BUS 0
|
||||
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */
|
||||
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10
|
||||
|
||||
|
||||
/* SD CARD gpio */
|
||||
|
@ -64,12 +64,12 @@
|
|||
#define AUDIO_CODEC_DDN "Maxim 98090 Codec "
|
||||
#define AUDIO_CODEC_I2C_ADDR 0x10
|
||||
|
||||
#define TI_SWITCH_HID "104C227E"
|
||||
#define TI_SWITCH_CID "104C227E"
|
||||
#define TI_SWITCH_DDN "TI SWITCH "
|
||||
#define TI_SWITCH_HID "104C227E"
|
||||
#define TI_SWITCH_CID "104C227E"
|
||||
#define TI_SWITCH_DDN "TI SWITCH "
|
||||
#define TI_SWITCH_I2C_ADDR 0x3B
|
||||
|
||||
#endif
|
||||
|
||||
#define DPTF_CPU_PASSIVE 88
|
||||
#define DPTF_CPU_CRITICAL 90
|
||||
|
||||
#endif
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corp.
|
||||
* Copyright (C) 2017 Matt DeVillier
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <mainboard/google/cyan/spd/spd_util.h>
|
||||
|
||||
/*
|
||||
* 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
|
||||
* 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz
|
||||
* 0b0010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
|
||||
* 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz
|
||||
* 0b0100 - 4GiB total - 2 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz
|
||||
* 0b0101 - 4GiB total - 2 x 2GiB Micron MT41K256M16TW-107 1600MHz
|
||||
* 0b0110 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz
|
||||
* 0b0111 - 2GiB total - 1 x 2GiB Micron MT41K256M16TW-107 1600MHz
|
||||
*/
|
||||
|
||||
int get_variant_spd_index(int ram_id, int *dual)
|
||||
{
|
||||
/* Determine if single or dual channel memory system */
|
||||
/* RAMID1 is deterministic for cyan */
|
||||
*dual = ((ram_id > 1) & 0x1) ? 0 : 1;
|
||||
|
||||
/* Display the RAM type */
|
||||
switch (ram_id) {
|
||||
case 0:
|
||||
printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646Q-HYK0 1600MHz\n");
|
||||
break;
|
||||
case 1:
|
||||
printk(BIOS_DEBUG, "4GiB Hynix H5TC4G63CFR-PBA 1600MHz\n");
|
||||
break;
|
||||
case 2:
|
||||
printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646Q-HYK0 1600MHz\n");
|
||||
break;
|
||||
case 3:
|
||||
printk(BIOS_DEBUG, "2GiB Hynix H5TC4G63CFR-PBA 1600MHz\n");
|
||||
break;
|
||||
case 4:
|
||||
printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646E-BYK0 1600MHz\n");
|
||||
break;
|
||||
case 5:
|
||||
printk(BIOS_DEBUG, "4GiB Micron MT41K256M16TW-107 1600MHz\n");
|
||||
break;
|
||||
case 6:
|
||||
printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646E-BYK0 1600MHz\n");
|
||||
break;
|
||||
case 7:
|
||||
printk(BIOS_DEBUG, "2GiB Micron MT41K256M16TW-107 1600MHz\n");
|
||||
break;
|
||||
}
|
||||
|
||||
/* 1:1 mapping between ram_id and spd_index for cyan */
|
||||
return ram_id;
|
||||
}
|
Loading…
Reference in New Issue