soc/intel/apollolake: Add functions to calculate GPIO address
Provide iosf and GPIO functions for GPIO address calculation. BUG=chrome-os-partner:55877 Change-Id: I6eaa1fcecf5970b365e3418541c75b9866959f7e Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16349 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -177,6 +177,16 @@ void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads)
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gpio_configure_pad(cfg + i);
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}
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void * gpio_dwx_address(const uint16_t pad)
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{
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/* Calculate Address of DW0 register for given GPIO
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* pad - GPIO number
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* returns - address of GPIO
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*/
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const struct pad_community *comm = gpio_get_community(pad);
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return iosf_address(comm->port, PAD_CFG_OFFSET(pad - comm->first_pad));
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}
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void gpio_input_pulldown(gpio_t gpio)
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{
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struct pad_config cfg = PAD_CFG_GPI(gpio, DN_20K, DEEP);
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@ -160,6 +160,8 @@ struct pad_config {
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void gpio_configure_pad(const struct pad_config *cfg);
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void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads);
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/* Calculate GPIO DW0 address */
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void * gpio_dwx_address(const uint16_t pad);
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/*
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* Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG
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* are passed which is then mapped to proper groups for MISCCFG. This basically
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@ -24,16 +24,19 @@
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#define RTC_CONFIG 0x3400
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#define RTC_CONFIG_UCMOS_ENABLE (1 << 2)
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static inline void * iosf_address(uint16_t port, uint16_t reg)
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{
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uintptr_t addr = (CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3));
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return (void *)addr;
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}
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inline static void iosf_write(uint16_t port, uint16_t reg, uint32_t val)
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{
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uintptr_t base = CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3);
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write32((void *)base, val);
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write32(iosf_address(port, reg), val);
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}
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inline static uint32_t iosf_read(uint16_t port, uint16_t reg)
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{
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uintptr_t base = CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3);
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return read32((void *)base);
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return read32(iosf_address(port, reg));
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}
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#endif /* _SOC_APOLLOLAKE_IOSF_H_ */
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