{soc, southbridge} : Correct typo in comment

BUG=N/A
TEST=N/A

Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32453
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/braswell/southcluster.c

@@ -347,7 +347,7 @@ static void sc_init(struct device *dev)
  * Common code for the south cluster devices.
  */
 
-/* Set bit in function disble register to hide this device. */
+/* Set bit in function disable register to hide this device. */
 static void sc_disable_devfn(struct device *dev)
 {
 	void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);

src/southbridge/intel/bd82x6x/pch.c

@@ -144,7 +144,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
 }
 
 #ifndef __SMM__
-/* Set bit in Function Disble register to hide this device */
+/* Set bit in function disable register to hide this device */
 static void pch_hide_devfn(unsigned devfn)
 {
 	switch (devfn) {

src/southbridge/intel/lynxpoint/pch.c

@@ -100,7 +100,7 @@ static void pch_enable_d3hot(struct device *dev)
 	pci_write_config32(dev, PCH_PCS, reg32);
 }
 
-/* Set bit in Function Disble register to hide this device */
+/* Set bit in function disable register to hide this device */
 void pch_disable_devfn(struct device *dev)
 {
 	switch (dev->path.pci.devfn) {