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{soc, southbridge} : Correct typo in comment 

BUG=N/A
TEST=N/A

Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32453
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Frans Hendriks 2019-05-01 10:48:31 +02:00 committed by Matt DeVillier
parent a88041c043
commit e6bf51fb22
3 changed files with 3 additions and 3 deletions
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2
src/soc/intel/braswell/southcluster.c
View File

@ -347,7 +347,7 @@ static void sc_init(struct device *dev)
* Common code for the south cluster devices. * Common code for the south cluster devices.
*/ */
/* Set bit in function disble register to hide this device. */ /* Set bit in function disable register to hide this device. */
static void sc_disable_devfn(struct device *dev) static void sc_disable_devfn(struct device *dev)
{ {
void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);

2
src/southbridge/intel/bd82x6x/pch.c
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@ -144,7 +144,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
} }
#ifndef __SMM__ #ifndef __SMM__
/* Set bit in Function Disble register to hide this device */ /* Set bit in function disable register to hide this device */
static void pch_hide_devfn(unsigned devfn) static void pch_hide_devfn(unsigned devfn)
{ {
switch (devfn) { switch (devfn) {

2
src/southbridge/intel/lynxpoint/pch.c
View File

@ -100,7 +100,7 @@ static void pch_enable_d3hot(struct device *dev)
pci_write_config32(dev, PCH_PCS, reg32); pci_write_config32(dev, PCH_PCS, reg32);
} }
/* Set bit in Function Disble register to hide this device */ /* Set bit in function disable register to hide this device */
void pch_disable_devfn(struct device *dev) void pch_disable_devfn(struct device *dev)
{ {
switch (dev->path.pci.devfn) { switch (dev->path.pci.devfn) {