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nb/intel/x4x/raminit: DDR3 specific ODT 

Change-Id: Ie32a008ce636b8eee6ed90c364978f7d37f4bfb2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19876
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2017-05-15 10:43:20 +02:00 committed by Patrick Georgi
parent 0d1c9b0e32
commit e6cc21e262
1 changed files with 37 additions and 5 deletions
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42
src/northbridge/intel/x4x/raminit_ddr23.c
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@ -1218,7 +1218,7 @@ static void prog_rcomp(struct sysinfo *s)
static void program_odt(struct sysinfo *s) static void program_odt(struct sysinfo *s)
{ {
u8 i; u8 i;
u16 odt[16][2] = { static u16 ddr2_odt[16][2] = {
{ 0x0000, 0x0000 }, // NC_NC { 0x0000, 0x0000 }, // NC_NC
{ 0x0000, 0x0001 }, // x8SS_NC { 0x0000, 0x0001 }, // x8SS_NC
{ 0x0000, 0x0011 }, // x8DS_NC { 0x0000, 0x0011 }, // x8DS_NC
@ -1237,11 +1237,43 @@ static void program_odt(struct sysinfo *s)
{ 0x0101, 0x0404 }, // x16SS_x16SS { 0x0101, 0x0404 }, // x16SS_x16SS
}; };
static const u16 ddr3_odt[16][2] = {
{ 0x0000, 0x0000 }, // NC_NC
{ 0x0000, 0x0001 }, // x8SS_NC
{ 0x0000, 0x0021 }, // x8DS_NC
{ 0x0000, 0x0001 }, // x16SS_NC
{ 0x0004, 0x0000 }, // NC_x8SS
{ 0x0105, 0x0405 }, // x8SS_x8SS
{ 0x0105, 0x4465 }, // x8DS_x8SS
{ 0x0105, 0x0405 }, // x16SS_x8SS
{ 0x0084, 0x0000 }, // NC_x8DS
{ 0x1195, 0x0405 }, // x8SS_x8DS
{ 0x1195, 0x4465 }, // x8DS_x8DS
{ 0x1195, 0x0405 }, // x16SS_x8DS
{ 0x0004, 0x0000 }, // NC_x16SS
{ 0x0105, 0x0405 }, // x8SS_x16SS
{ 0x0105, 0x4465 }, // x8DS_x16SS
{ 0x0105, 0x0405 }, // x16SS_x16SS
};
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
MCHBAR16(0x400*i + 0x298) = odt[s->dimm_config[i]][1]; if (s->spd_type == DDR2) {
MCHBAR16(0x400*i + 0x294) = odt[s->dimm_config[i]][0]; MCHBAR16(0x400 * i + 0x298) =
MCHBAR16(0x400*i + 0x29c) = (MCHBAR16(0x400*i + 0x29c) & ~0xfff) | 0x66b; ddr2_odt[s->dimm_config[i]][1];
MCHBAR32(0x400*i + 0x260) = (MCHBAR32(0x400*i + 0x260) & ~0x70e3c00) | 0x3063c00; MCHBAR16(0x400 * i + 0x294) =
ddr2_odt[s->dimm_config[i]][0];
} else {
MCHBAR16(0x400 * i + 0x298) =
ddr3_odt[s->dimm_config[i]][1];
MCHBAR16(0x400 * i + 0x294) =
ddr3_odt[s->dimm_config[i]][0];
}
u16 reg16 = MCHBAR16(0x400*i + 0x29c);
reg16 &= ~0xfff;
reg16 |= (s->spd_type == DDR2 ? 0x66b : 0x778);
MCHBAR16(0x400*i + 0x29c) = reg16;
MCHBAR32(0x400*i + 0x260) = (MCHBAR32(0x400*i + 0x260)
& ~0x70e3c00) | 0x3063c00;
} }
} }