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mb/hp/280_g2/devicetree: Use comma separated list for arrays 

In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they should stay in
the devicetree at their related root ports.

Change-Id: I85f7c0ddebf88dd21e6c2603ce45f0a4fc868d51
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78600
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2023-10-23 17:15:34 +02:00 committed by Felix Held
parent eb1a2bd132
commit e6f19240de
1 changed files with 28 additions and 25 deletions
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53
src/mainboard/hp/280_g2/devicetree.cb
View File

@ -16,31 +16,34 @@ chip soc/intel/skylake
device pci 04.0 on end # CPU Thermal
device pci 08.0 on end # GMM
device pci 14.0 on # xHCI
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC0),
[1] = USB2_PORT_MID(OC0),
[2] = USB2_PORT_MID(OC4),
[3] = USB2_PORT_MID(OC4),
[4] = USB2_PORT_MID(OC2),
[5] = USB2_PORT_MID(OC2),
[6] = USB2_PORT_MID(OC0),
[7] = USB2_PORT_MID(OC0),
[8] = USB2_PORT_MID(OC0),
[9] = USB2_PORT_MID(OC0),
[10] = USB2_PORT_MID(OC1),
[11] = USB2_PORT_MID(OC1),
[12] = USB2_PORT_MID(OC_SKIP),
[13] = USB2_PORT_MID(OC_SKIP),
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0),
[1] = USB3_PORT_DEFAULT(OC0),
[2] = USB3_PORT_DEFAULT(OC3),
[3] = USB3_PORT_DEFAULT(OC3),
[4] = USB3_PORT_DEFAULT(OC1),
[5] = USB3_PORT_DEFAULT(OC1),
[6] = USB3_PORT_DEFAULT(OC_SKIP),
[7] = USB3_PORT_DEFAULT(OC_SKIP),
[8] = USB3_PORT_DEFAULT(OC_SKIP),
[9] = USB3_PORT_DEFAULT(OC_SKIP),
}"
end
device pci 14.1 off end # USB OTG
device pci 14.2 on end # PCH Thermal