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apollolake: Update UPD header files for FSP 1.3.0 

These updated header files contain USB tuning parameters as well as
some general cleanup of unused parameters in the UPD Headers. This
patch along with the upcoming FSP 1.3.0 release will allow for USB
tuning on apollolake platforms.

CQ-DEPEND=CL:*315403
BUG=chrome-os-partner:61031

Change-Id: Id7cce1ea83057630d508523ada18c5425804535e
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/18046
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Brandon Breitenstein 2017-01-05 12:47:27 -08:00 committed by Aaron Durbin
parent 9bafa2947b
commit e7056a82e0
2 changed files with 44 additions and 73 deletions
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36
src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h
View File

@ -820,32 +820,6 @@ typedef struct {
UINT8 ReservedFspmUpd[12];
} FSP_M_CONFIG;
/** Fsp M Test Configuration
**/
typedef struct {
/** Offset 0x0160
**/
UINT32 Signature;
/** Offset 0x0164
**/
UINT8 ReservedFspmTestUpd[12];
} FSP_M_TEST_CONFIG;
/** Fsp M Restricted Configuration
**/
typedef struct {
/** Offset 0x0170
**/
UINT32 Signature;
/** Offset 0x0174
**/
UINT8 ReservedFspmRestrictedUpd[124];
} FSP_M_RESTRICTED_CONFIG;
/** Fsp M UPD Configuration
**/
typedef struct {
@ -864,15 +838,7 @@ typedef struct {
/** Offset 0x0160
**/
FSP_M_TEST_CONFIG FspmTestConfig;
/** Offset 0x0170
**/
FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;
/** Offset 0x01F0
**/
UINT8 UnusedUpdSpace2[14];
UINT8 UnusedUpdSpace2[158];
/** Offset 0x01FE
**/

81
src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h
View File

@ -1521,35 +1521,48 @@ typedef struct {
/** Offset 0x0334
**/
UINT8 ReservedFspsUpd[12];
UINT8 UnusedUpdSpace7[4];
/** Offset 0x0338 - PerPort Half Bit Pre-emphasis
PerPort Half Bit Pre-emphasis. Value of register USB2_PER_PORT_PPX [14]
**/
UINT8 PortUsb20PerPortTxPeHalf[8];
/** Offset 0x0340 - PerPort HS Pre-emphasis Bias
PerPort HS Pre-emphasis Bias. Value of register USB2_PER_PORT_PPX [13:11]
**/
UINT8 PortUsb20PerPortPeTxiSet[8];
/** Offset 0x0348 - PerPort HS Transmitter Bias
PerPort HS Transmitter Bias. Value of register USB2_PER_PORT_PPX [10:8]
**/
UINT8 PortUsb20PerPortTxiSet[8];
/** Offset 0x0350 - Select the skew direction for HS transition
Select the skew direction for HS transition. Value of register USB2_PER_PORT_2_PPX [25]
**/
UINT8 PortUsb20HsSkewSel[8];
/** Offset 0x0358 - Per Port HS Transmitter Emphasis
Per Port HS Transmitter Emphasis. Value of register USB2_PER_PORT_2_PPX [24:23]
**/
UINT8 PortUsb20IUsbTxEmphasisEn[8];
/** Offset 0x0360 - PerPort HS Receiver Bias
PerPort HS Receiver Bias. Value of register USB2_PER_PORT_2_PPX [19:17]
**/
UINT8 PortUsb20PerPortRXISet[8];
/** Offset 0x0368 - Delay/skew's strength control for HS driver
Delay/skew's strength control for HS driver. Value of register USB2_PER_PORT_2_PPX [1:0]
**/
UINT8 PortUsb20HsNpreDrvSel[8];
/** Offset 0x0370
**/
UINT8 ReservedFspsUpd[16];
} FSP_S_CONFIG;
/** Fsp S Test Configuration
**/
typedef struct {
/** Offset 0x0340
**/
UINT32 Signature;
/** Offset 0x0344
**/
UINT8 ReservedFspsTestUpd[12];
} FSP_S_TEST_CONFIG;
/** Fsp S Restricted Configuration
**/
typedef struct {
/** Offset 0x0350
**/
UINT32 Signature;
/** Offset 0x0354
**/
UINT8 ReservedFspsRestrictedUpd[12];
} FSP_S_RESTRICTED_CONFIG;
/** Fsp S UPD Configuration
**/
typedef struct {
@ -1562,19 +1575,11 @@ typedef struct {
**/
FSP_S_CONFIG FspsConfig;
/** Offset 0x0340
/** Offset 0x0380
**/
FSP_S_TEST_CONFIG FspsTestConfig;
UINT8 UnusedUpdSpace8[46];
/** Offset 0x0350
**/
FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig;
/** Offset 0x0360
**/
UINT8 UnusedUpdSpace7[14];
/** Offset 0x036E
/** Offset 0x03AE
**/
UINT16 UpdTerminator;
} FSPS_UPD;