From e7089e12a13e96e61216d94db85a1c6a1347449d Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 13 Apr 2022 11:58:08 +0530 Subject: [PATCH] soc/intel/cmn/gpmr: Enhance GPMR driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch enhances the GPMR driver to add public APIs for other IA common code drivers and/or SoC code to utilize. Also, migrated all PCR GPMR register definitions into the common `pcr_gpmr.h` header file. TEST=Able to build and boot google/redrix. Signed-off-by: Subrata Banik Change-Id: I87dca55a068366cb9a26a5218589166c1723da7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63607 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/soc/intel/common/block/gpmr/gpmr.c | 10 +++++-- .../common/block/include/intelblocks/gpmr.h | 14 ++++++++++ .../block/include/intelblocks/pcr_gpmr.h | 27 +++++++++++++++++++ 3 files changed, 49 insertions(+), 2 deletions(-) create mode 100644 src/soc/intel/common/block/include/intelblocks/gpmr.h create mode 100644 src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h diff --git a/src/soc/intel/common/block/gpmr/gpmr.c b/src/soc/intel/common/block/gpmr/gpmr.c index 1a3a6023d6..d0fe499be0 100644 --- a/src/soc/intel/common/block/gpmr/gpmr.c +++ b/src/soc/intel/common/block/gpmr/gpmr.c @@ -2,6 +2,7 @@ #include #include +#include #include #include @@ -16,17 +17,22 @@ #define DMI_PCR_GPMR_EN BIT(31) /* GPMR Register read given offset */ -static uint32_t gpmr_read32(uint16_t offset) +uint32_t gpmr_read32(uint16_t offset) { return pcr_read32(PID_DMI, offset); } /* GPMR Register write given offset and val */ -static void gpmr_write32(uint16_t offset, uint32_t val) +void gpmr_write32(uint16_t offset, uint32_t val) { return pcr_write32(PID_DMI, offset, val); } +void gpmr_or32(uint16_t offset, uint32_t ordata) +{ + return pcr_or32(PID_DMI, offset, ordata); +} + /* Check for available free gpmr */ static int get_available_gpmr(void) { diff --git a/src/soc/intel/common/block/include/intelblocks/gpmr.h b/src/soc/intel/common/block/include/intelblocks/gpmr.h new file mode 100644 index 0000000000..d898f329b8 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/gpmr.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_GPMR_H +#define SOC_INTEL_COMMON_BLOCK_GPMR_H + +#include +#include + +uint32_t gpmr_read32(uint16_t offset); +void gpmr_write32(uint16_t offset, uint32_t val); +void gpmr_or32(uint16_t offset, uint32_t ordata); +enum cb_err enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id); + +#endif /* SOC_INTEL_COMMON_BLOCK_GPMR_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h b/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h new file mode 100644 index 0000000000..fb138f91a0 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_PCR_GPMR_H +#define SOC_INTEL_COMMON_BLOCK_PCR_GPMR_H + +#define GPMR_LPCLGIR1 0x2730 +#define GPMR_DMICTL 0x2234 +#define GPMR_DMICTL_SRLOCK (1 << 31) +#define GPMR_LPCGMR 0x2740 +#define GPMR_GCS 0x274c +#define GPMR_GCS_BILD (1 << 0) +#define GPMR_LPCIOD 0x2770 +#define GPMR_LPCIOE 0x2774 +#define GPMR_TCOBASE 0x2778 +#define GPMR_TCOEN (1 << 1) + +#define MAX_GPMR_REGS 3 + +#define GPMR_OFFSET(x) (0x277c + (x) * 8) +#define GPMR_LIMIT_MASK 0xffff0000 +#define GPMR_BASE_SHIFT 16 +#define GPMR_BASE_MASK 0xffff + +#define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) +#define GPMR_EN BIT(31) + +#endif /* SOC_INTEL_COMMON_BLOCK_PCR_GPMR_H */