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soc/apollolake: Add CSE Firmware Status Registers 

Add the CSE, General Status and Miscellaneous registers and
print information from them accordingly. All values were taken
from Intel document number 571993.

Tested on the StarLite Mk III and the correct values are
shown:
   [DEBUG]  CSE: Working State          : 2
   [DEBUG]  CSE: Manufacturing Mode     : NO
   [DEBUG]  CSE: Operation State        : 1
   [DEBUG]  CSE: FW Init Complete       : NO
   [DEBUG]  CSE: Error Code             : 3
   [DEBUG]  CSE: Operation Mode         : 0
   [DEBUG]  CSE: FPF status              : unknown

Please note, the values shown are in an error state.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1a5548132dadbb188a33a7ae30a0a1fa144d130f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Sean Rhodes 2022-07-19 11:20:05 +01:00 committed by Felix Held
parent 759bb4c00d
commit e71ea1e1b6
2 changed files with 80 additions and 8 deletions
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24
src/soc/intel/apollolake/cse.c
View File

@ -8,6 +8,7 @@
#include <intelblocks/cse.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <soc/cse.h>
#include <soc/heci.h>
#include <soc/iomap.h>
#include <soc/pcr_ids.h>
@ -156,25 +157,32 @@ static uint32_t dump_status(int index, int reg_addr)
static void dump_cse_state(void)
{
uint32_t fwsts1;
union cse_fwsts1 fwsts1;
if (!is_cse_enabled())
return;
fwsts1 = dump_status(1, PCI_ME_HFSTS1);
fwsts1.data = dump_status(1, PCI_ME_HFSTS1);
dump_status(2, PCI_ME_HFSTS2);
dump_status(3, PCI_ME_HFSTS3);
dump_status(4, PCI_ME_HFSTS4);
dump_status(5, PCI_ME_HFSTS5);
dump_status(6, PCI_ME_HFSTS6);
/* Minimal decoding is done here in order to call out most important
pieces. Manufacturing mode needs to be locked down prior to shipping
the product so it's called out explicitly. */
printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n",
(fwsts1 & (1 << 0x4)) ? "YES" : "NO");
printk(BIOS_DEBUG, "CSE: Working State : %u\n",
fwsts1.fields.working_state);
printk(BIOS_DEBUG, "CSE: Manufacturing Mode : %s\n",
fwsts1.fields.mfg_mode ? "YES" : "NO");
printk(BIOS_DEBUG, "CSE: Operation State : %u\n",
fwsts1.fields.operation_state);
printk(BIOS_DEBUG, "CSE: FW Init Complete : %s\n",
fwsts1.fields.fw_init_complete ? "YES" : "NO");
printk(BIOS_DEBUG, "CSE: Error Code : %u\n",
fwsts1.fields.error_code);
printk(BIOS_DEBUG, "CSE: Operation Mode : %u\n",
fwsts1.fields.operation_mode);
printk(BIOS_DEBUG, "ME: FPF status : ");
printk(BIOS_DEBUG, "CSE: FPF status : ");
switch (g_fuse_state) {
case FUSE_FLASH_UNFUSED:
printk(BIOS_DEBUG, "unfused");

64
src/soc/intel/apollolake/include/soc/cse.h Normal file
View File

@ -0,0 +1,64 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _APOLLOLAKE_CSE_H_
#define _APOLLOLAKE_CSE_H_
/* CSE Host Firmware Status register 1 */
union cse_fwsts1 {
uint32_t data;
struct {
uint32_t working_state: 4;
uint32_t mfg_mode: 1;
uint32_t fpt_bad: 1;
uint32_t operation_state: 3;
uint32_t fw_init_complete: 1;
uint32_t ft_bup_ld_flr: 1;
uint32_t update_in_progress: 1;
uint32_t error_code: 4;
uint32_t operation_mode: 4;
uint32_t reserved: 4;
uint32_t boot_options_present: 1;
uint32_t ack_data: 3;
uint32_t bios_message_ack: 4;
} __packed fields;
};
/* Miscellaneous Shadow Register 1 */
union cse_fwsts2 {
uint32_t data;
struct {
uint32_t cse_uma_size: 6;
uint32_t reserved1: 8;
uint32_t reserved2: 2;
uint32_t cse_uma_size_valid: 1;
uint32_t reserved3: 8;
uint32_t reserved4: 6;
uint32_t misc_shadow_valid: 1;
} __packed fields;
};
/* General Status Shadow Register */
union cse_fwsts3 {
uint32_t data;
struct {
uint32_t bist_in_progress: 1;
uint32_t icc_prog_sts: 2;
uint32_t invoke_mebx: 1;
uint32_t cpu_replaced_sts: 1;
uint32_t mbp_ready: 1;
uint32_t mfs_failure: 1;
uint32_t warm_rst_req_for_df: 1;
uint32_t cpu_replaced_valid: 1;
uint32_t reserved1: 2;
uint32_t fw_upd_ipu: 1;
uint32_t reserved2: 1;
uint32_t mbp_cleared: 1;
uint32_t reserved3: 2;
uint32_t ext_stat_code1: 8;
uint32_t ext_stat_code2: 4;
uint32_t infra_phase_code: 4;
} __packed fields;
};
#endif /* _APOLLOLAKE_CSE_H_ */