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Enable 33 MHz fast mode SPI read early to reduce boot time. 

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2011-05-15 21:48:22 +00:00 committed by Marc Jones
parent 9ab3c6c3a9
commit e73fc20886
1 changed files with 13 additions and 0 deletions
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13
src/mainboard/amd/persimmon/romstage.c
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@ -47,6 +47,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
u8 reg8;
// early enable of SPI 33 MHz fast mode read
if (boot_cpu())
{
volatile u32 *spiBase = (void *) 0xa0000000;
u32 save;
__outdword (0xcf8, 0x8000a3a0);
save = __indword (0xcfc);
__outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
spiBase [0] |= 1 << 18; // fast read enable
__outdword (0xcfc, save); // clear temp base
}
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_poweron_init();