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cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSx 

This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures
Software Developer’s Manual.

The purpose is to differentiate with MSR_SMRR_PHYSx.

Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Arthur Heymans 2018-07-20 23:31:59 +02:00 committed by Patrick Georgi
parent 6b27c38f4a
commit e750b38e48
12 changed files with 24 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/intel/haswell/smmrelocate.c
View File

@ -70,8 +70,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{ {
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo); relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
} }
static inline void write_emrr(struct smm_relocation_params *relo_params) static inline void write_emrr(struct smm_relocation_params *relo_params)

4
src/cpu/intel/smm/gen1/smmrelocate.c
View File

@ -61,8 +61,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{ {
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo); relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
} }
/* The relocation work is actually performed in SMM context, but the code /* The relocation work is actually performed in SMM context, but the code

4
src/include/cpu/x86/mtrr.h
View File

@ -28,8 +28,8 @@
#define MTRR_DEF_TYPE_FIX_EN (1 << 10) #define MTRR_DEF_TYPE_FIX_EN (1 << 10)
#define SMRR_PHYS_BASE 0x1f2 #define IA32_SMRR_PHYS_BASE 0x1f2
#define SMRR_PHYS_MASK 0x1f3 #define IA32_SMRR_PHYS_MASK 0x1f3
#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) #define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))
#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) #define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)

4
src/soc/intel/apollolake/cpu.c
View File

@ -223,10 +223,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
/* Set up SMRR. */ /* Set up SMRR. */
smrr.lo = relo_attrs.smrr_base; smrr.lo = relo_attrs.smrr_base;
smrr.hi = 0; smrr.hi = 0;
wrmsr(SMRR_PHYS_BASE, smrr); wrmsr(IA32_SMRR_PHYS_BASE, smrr);
smrr.lo = relo_attrs.smrr_mask; smrr.lo = relo_attrs.smrr_mask;
smrr.hi = 0; smrr.hi = 0;
wrmsr(SMRR_PHYS_MASK, smrr); wrmsr(IA32_SMRR_PHYS_MASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
smm_state->smbase = staggered_smbase; smm_state->smbase = staggered_smbase;
} }

4
src/soc/intel/baytrail/cpu.c
View File

@ -179,10 +179,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
/* Set up SMRR. */ /* Set up SMRR. */
smrr.lo = relo_attrs.smrr_base; smrr.lo = relo_attrs.smrr_base;
smrr.hi = 0; smrr.hi = 0;
wrmsr(SMRR_PHYS_BASE, smrr); wrmsr(IA32_SMRR_PHYS_BASE, smrr);
smrr.lo = relo_attrs.smrr_mask; smrr.lo = relo_attrs.smrr_mask;
smrr.hi = 0; smrr.hi = 0;
wrmsr(SMRR_PHYS_MASK, smrr); wrmsr(IA32_SMRR_PHYS_MASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
smm_state->smbase = staggered_smbase; smm_state->smbase = staggered_smbase;

4
src/soc/intel/braswell/cpu.c
View File

@ -195,10 +195,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
/* Set up SMRR. */ /* Set up SMRR. */
smrr.lo = relo_attrs.smrr_base; smrr.lo = relo_attrs.smrr_base;
smrr.hi = 0; smrr.hi = 0;
wrmsr(SMRR_PHYS_BASE, smrr); wrmsr(IA32_SMRR_PHYS_BASE, smrr);
smrr.lo = relo_attrs.smrr_mask; smrr.lo = relo_attrs.smrr_mask;
smrr.hi = 0; smrr.hi = 0;
wrmsr(SMRR_PHYS_MASK, smrr); wrmsr(IA32_SMRR_PHYS_MASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
smm_state->smbase = staggered_smbase; smm_state->smbase = staggered_smbase;

4
src/soc/intel/broadwell/smmrelocate.c
View File

@ -38,8 +38,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{ {
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo); relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
} }
static inline void write_emrr(struct smm_relocation_params *relo_params) static inline void write_emrr(struct smm_relocation_params *relo_params)

4
src/soc/intel/cannonlake/smmrelocate.c
View File

@ -41,8 +41,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{ {
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo); relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
} }
static void update_save_state(int cpu, uintptr_t curr_smbase, static void update_save_state(int cpu, uintptr_t curr_smbase,

4
src/soc/intel/denverton_ns/cpu.c
View File

@ -80,10 +80,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
/* Set up SMRR. */ /* Set up SMRR. */
smrr.lo = relo_attrs.smrr_base; smrr.lo = relo_attrs.smrr_base;
smrr.hi = 0; smrr.hi = 0;
wrmsr(SMRR_PHYS_BASE, smrr); wrmsr(IA32_SMRR_PHYS_BASE, smrr);
smrr.lo = relo_attrs.smrr_mask; smrr.lo = relo_attrs.smrr_mask;
smrr.hi = 0; smrr.hi = 0;
wrmsr(SMRR_PHYS_MASK, smrr); wrmsr(IA32_SMRR_PHYS_MASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
smm_state->smbase = staggered_smbase; smm_state->smbase = staggered_smbase;
} }

4
src/soc/intel/fsp_baytrail/cpu.c
View File

@ -139,10 +139,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
/* Set up SMRR. */ /* Set up SMRR. */
smrr.lo = relo_attrs.smrr_base; smrr.lo = relo_attrs.smrr_base;
smrr.hi = 0; smrr.hi = 0;
wrmsr(SMRR_PHYS_BASE, smrr); wrmsr(IA32_SMRR_PHYS_BASE, smrr);
smrr.lo = relo_attrs.smrr_mask; smrr.lo = relo_attrs.smrr_mask;
smrr.hi = 0; smrr.hi = 0;
wrmsr(SMRR_PHYS_MASK, smrr); wrmsr(IA32_SMRR_PHYS_MASK, smrr);
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
smm_state->smbase = staggered_smbase; smm_state->smbase = staggered_smbase;

4
src/soc/intel/fsp_broadwell_de/smmrelocate.c
View File

@ -39,8 +39,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{ {
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo); relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
} }
static inline void write_prmrr(struct smm_relocation_params *relo_params) static inline void write_prmrr(struct smm_relocation_params *relo_params)

4
src/soc/intel/skylake/smmrelocate.c
View File

@ -41,8 +41,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{ {
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo); relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base); wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask); wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
} }
static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)