From e7537f134d8484f3b8560e00a838bdacce4ea884 Mon Sep 17 00:00:00 2001 From: Torsten Duwe Date: Wed, 31 Oct 2007 00:49:38 +0000 Subject: [PATCH] As started in http://www.linuxbios.org/pipermail/linuxbios/2007-October/025385.html , but change all apparantly related values that differ on my board with legacy BIOS. This makes both PCI cards appear, as well as the firewire device TSB43AB23. * PCI 01:07.0 appears fully functional * PCI 01:08.0 (closer to the board edge) appears, but no interrupts * PCI 01:0a.0 (FireWire) untested Since none of these was even present without the patch I suggest to apply it. Signed-off-by: Torsten Duwe Acked-by: Carl-Daniel Hailfinger Tested-by: Harald Gutmann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c index c39f626d28..3a17ef2d2f 100644 --- a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c +++ b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c @@ -134,10 +134,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define MCP55_PCI_E_X_0 0 #define MCP55_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */