northbridge/intel/i945: Fix GCC optimizing out cache preload jump

Clock config setup must be run from cache. Original code used "goto"
to prefetch the code required to update the VCO (by jumping after
the code and back before). The GCC since at least 12.1.0 and clang
since at least 13.0.1 will elimitate these jumps.

Use inline assembler to force the original code flow.

TEST=Verified assembly code is the same as generated by GCC 12.1.0
and boot tested on Kontron 986LCD-M.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: I67c2072b5983a5bd845631af136ae5a003c7ea3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/i945/raminit.c

@@ -1771,9 +1771,20 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
 
 	mchbar_write32(CLKCFG, clkcfg);
 
-	/* Make sure the following code is in the cache before we execute it. */
+	/*
-	goto cache_code;
+	 * Make sure the following code is in the cache before we execute it.
-vco_update:
+	 * TODO: Experiments (i945GM) without any cache_code/delay_update
+	 * _seem_ to work even when XIP is disabled. Also on Pentium 4
+	 * the code is not cached at all by default.
+	 */
+	asm volatile (
+		"	jmp cache_code\n"
+		"vco_update:\n"
+		: /* No outputs */
+		: /* No inputs */
+		: "memory"
+	);
+
 	pci_and_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, (u8)~(1 << 7));
 
 	clkcfg &= ~(1 << 10);
@@ -1797,10 +1808,15 @@ vco_update:
 	clkcfg &= ~(1 << 10);
 	mchbar_write32(CLKCFG, clkcfg);
 
-	goto out;
+	asm volatile (
-cache_code:
+		"	jmp out\n"
-	goto vco_update;
+		"cache_code:\n"
-out:
+		"	jmp vco_update\n"
+		"out:\n"
+		: /* No outputs */
+		: /* No inputs */
+		: "memory"
+	);
 
 	printk(BIOS_DEBUG, "CLKCFG = 0x%08x, ", mchbar_read32(CLKCFG));
 	printk(BIOS_DEBUG, "ok\n");