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superio/nsc: Introduce common early_serial 

Change-Id: I0860e95258b87f059a3a9c31e382d758403d0428
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Peter Lemenkov 2019-02-10 23:03:17 +01:00 committed by Patrick Georgi
parent 85ea91ae3c
commit e7705f2df1
4 changed files with 80 additions and 0 deletions
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4
src/superio/nsc/Makefile.inc
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@ -13,6 +13,10 @@
## GNU General Public License for more details.
##
## include generic nsc pre-ram stage driver
bootblock-$(CONFIG_SUPERIO_NSC_COMMON_PRE_RAM) += common/early_serial.c
romstage-$(CONFIG_SUPERIO_NSC_COMMON_PRE_RAM) += common/early_serial.c
subdirs-y += pc87309
subdirs-y += pc87360
subdirs-y += pc87366

19
src/superio/nsc/common/Kconfig Normal file
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@ -0,0 +1,19 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
# Generic NSC romstage driver - Just enough UART initialisation code for
# pre-ram.
config SUPERIO_NSC_COMMON_PRE_RAM
bool

31
src/superio/nsc/common/early_serial.c Normal file
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@ -0,0 +1,31 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000 AG Electronics Ltd.
* Copyright (C) 2003-2004 Linux Networx
* Copyright (C) 2004 Tyan
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <device/pnp_def.h>
#include <stdint.h>
#include "nsc.h"
void nsc_enable_serial(pnp_devfn_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}

26
src/superio/nsc/common/nsc.h Normal file
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@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
* Copyright (C) 2014 Felix Held <felix-coreboot@felixheld.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SUPERIO_NSC_COMMON_PRE_RAM_H
#define SUPERIO_NSC_COMMON_PRE_RAM_H
#include <device/pnp_def.h>
#include <stdint.h>
void nsc_enable_serial(pnp_devfn_t dev, u16 iobase);
#endif /* SUPERIO_NSC_COMMON_PRE_RAM_H */