soc/intel/apollolake: Add reset code to postcar stage
Also add a test case for that, a config taken from chromiumos with some references to binaries dropped that aren't in our blobs repo (eg audio firmware). Change-Id: I411c0bacefd9345326f26db4909921dddba28237 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/29223 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -0,0 +1,15 @@
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CONFIG_USE_BLOBS=y
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CONFIG_VENDOR_GOOGLE=y
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CONFIG_BOARD_GOOGLE_REEF=y
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CONFIG_CHROMEOS=y
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CONFIG_ADD_FSP_BINARIES=y
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CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
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CONFIG_ELOG_GSMI=y
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CONFIG_ELOG_BOOT_COUNT=y
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CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
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CONFIG_SPI_FLASH_SMM=y
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# CONFIG_CONSOLE_SERIAL is not set
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CONFIG_CMOS_POST=y
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CONFIG_CMOS_POST_OFFSET=0x70
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CONFIG_CMOS_POST_EXTRA=y
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CONFIG_PAYLOAD_NONE=y
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@ -72,6 +72,8 @@ postcar-y += memmap.c
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postcar-y += mmap_boot.c
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postcar-y += mmap_boot.c
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postcar-y += spi.c
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postcar-y += spi.c
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postcar-y += i2c.c
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postcar-y += i2c.c
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postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c
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postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c
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postcar-$(CONFIG_UART_DEBUG) += uart.c
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postcar-$(CONFIG_UART_DEBUG) += uart.c
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postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
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postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
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