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Configure CIMx to use 33 MHz fast mode for SPD read. 

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2011-05-15 21:18:59 +00:00 committed by Marc Jones
parent 444c49c68c
commit e78ae24eb1
1 changed files with 2 additions and 2 deletions
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4
src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h
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@ -116,8 +116,8 @@ typedef union _PCI_ADDR {
#define cimHpetTimerDefault TRUE #define cimHpetTimerDefault TRUE
#define cimHpetMsiDisDefault FALSE // Enable #define cimHpetMsiDisDefault FALSE // Enable
#define cimIrConfigDefault 0x00 // Disable #define cimIrConfigDefault 0x00 // Disable
#define cimSpiFastReadEnableDefault 0x00 // Disable #define cimSpiFastReadEnableDefault 0x01 // Enable
#define cimSpiFastReadSpeedDefault 0x00 // NULL #define cimSpiFastReadSpeedDefault 0x01 // 33 MHz
// GPP/AB Controller // GPP/AB Controller
#define cimNbSbGen2Default TRUE #define cimNbSbGen2Default TRUE
#define cimAlinkPhyPllPowerDownDefault TRUE #define cimAlinkPhyPllPowerDownDefault TRUE