mediatek/mt8183: postpone dcxo low power mode setting

Consider the association between modem[1] and DCXO, this patch is a fix for
eb5e47d("mediatek/mt8183: update dcxo output buffer setting") [2]
We should not disable XO_CEL and block the bblpm request when modem is still ON.
For power-saving, we still could disable unused XO_CEL and
mask request to disable unused power mode when modem is no longer be used.

[1] https://review.coreboot.org/c/coreboot/+/32666
[2] https://review.coreboot.org/c/coreboot/+/32323

BRANCH=none
TEST=Boots correctly on Krane.

Change-Id: I047ebed615e874977ca211aafd52b5551c71b764
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Weiyi Lu 2019-08-05 17:45:24 +08:00 committed by Patrick Georgi
parent bcbf2deb42
commit e78d140b11
3 changed files with 14 additions and 3 deletions

View File

@ -147,6 +147,7 @@ enum {
/* PMIC DCXO Register Definition */ /* PMIC DCXO Register Definition */
enum { enum {
PMIC_RG_DCXO_CW00 = 0x0788, PMIC_RG_DCXO_CW00 = 0x0788,
PMIC_RG_DCXO_CW00_CLR = 0x078C,
PMIC_RG_DCXO_CW02 = 0x0790, PMIC_RG_DCXO_CW02 = 0x0790,
PMIC_RG_DCXO_CW07 = 0x079A, PMIC_RG_DCXO_CW07 = 0x079A,
PMIC_RG_DCXO_CW09 = 0x079E, PMIC_RG_DCXO_CW09 = 0x079E,
@ -218,5 +219,6 @@ void rtc_bbpu_power_on(void);
void rtc_osc_init(void); void rtc_osc_init(void);
int rtc_init(u8 recover); int rtc_init(u8 recover);
void rtc_boot(void); void rtc_boot(void);
void mt6358_dcxo_disable_unused(void);
#endif /* SOC_MEDIATEK_MT8183_RTC_H */ #endif /* SOC_MEDIATEK_MT8183_RTC_H */

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@ -411,10 +411,9 @@ static void dcxo_init(void)
rtc_write(PMIC_RG_DCXO_CW16, 0x9855); rtc_write(PMIC_RG_DCXO_CW16, 0x9855);
/* 26M enable control */ /* 26M enable control */
/* Enable clock buffer XO_SOC */ /* Enable clock buffer XO_SOC, XO_CEL */
rtc_write(PMIC_RG_DCXO_CW00, 0x4005); rtc_write(PMIC_RG_DCXO_CW00, 0x4805);
rtc_write(PMIC_RG_DCXO_CW11, 0x8000); rtc_write(PMIC_RG_DCXO_CW11, 0x8000);
rtc_write(PMIC_RG_DCXO_CW23, 0x0053);
/* Load thermal coefficient */ /* Load thermal coefficient */
rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7);
@ -432,6 +431,14 @@ static void dcxo_init(void)
mdelay(5); mdelay(5);
} }
void mt6358_dcxo_disable_unused(void)
{
/* Disable clock buffer XO_CEL */
rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800);
/* Mask bblpm */
rtc_write(PMIC_RG_DCXO_CW23, 0x0053);
}
/* the rtc boot flow entry */ /* the rtc boot flow entry */
void rtc_boot(void) void rtc_boot(void)
{ {

View File

@ -17,6 +17,7 @@
#include <soc/emi.h> #include <soc/emi.h>
#include <soc/md_ctrl.h> #include <soc/md_ctrl.h>
#include <soc/mmu_operations.h> #include <soc/mmu_operations.h>
#include <soc/rtc.h>
#include <soc/sspm.h> #include <soc/sspm.h>
#include <symbols.h> #include <symbols.h>
@ -29,6 +30,7 @@ static void soc_init(struct device *dev)
{ {
mtk_mmu_disable_l2c_sram(); mtk_mmu_disable_l2c_sram();
mtk_md_early_init(); mtk_md_early_init();
mt6358_dcxo_disable_unused();
sspm_init(); sspm_init();
} }