qualcomm/sc7180: Switch to common MIPI panel library
This patch changes the sc7180 boards to use the new common MIPI panel framework, which allows more flexible initialization command packing and sharing panel definitions between boards. (I'm taking the lane count control back out again for now, since it seems we only ever want 4 for now anyway, and if we ever have a need for a different lane count it's not clear whether that should be a property of the board or the panel or both. Better to leave that decision until we have a real use case.) Also, the code was not written to deal with DCS commands that were not a length divisible by 4 (it would read over the end of the command buffer). The corresponding kernel driver seems to pad the command with 0xff instead, let's do the same here. (Also increase the maximum allowed command length to 256 bytes, as per Qualcomm's recommendation.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56966 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Julius Werner
parent
312fb716d0
commit
e78fd115e6
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@ -35,3 +35,6 @@ config MIPI_PANEL_INX_OTA7290D10P
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config MIPI_PANEL_STA_2081101QFH032011_53G
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bool
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config MIPI_PANEL_VIS_RM69299
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bool
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@ -20,6 +20,8 @@ panel-params-$(CONFIG_MIPI_PANEL_INX_OTA7290D10P) += panel-INX_OTA7290D10P
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panel-params-$(CONFIG_MIPI_PANEL_STA_2081101QFH032011_53G) += panel-STA_2081101QFH032011_53G
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panel-params-$(CONFIG_MIPI_PANEL_VIS_RM69299) += panel-VIS_RM69299
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$(foreach params,$(panel-params-y), \
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$(eval cbfs-files-y += $(params)) \
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$(eval $(params)-file := $(params).c:struct) \
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@ -0,0 +1,33 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mipi_panel.h>
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struct panel_serializable_data VIS_RM69299 = {
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.edid = {
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.ascii_string = "RM69299",
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.manufacturer_name = "RM",
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.panel_bits_per_color = 8,
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.panel_bits_per_pixel = 24,
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.mode = {
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.pixel_clock = 158695,
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.lvds_dual_channel = 0,
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.refresh = 60,
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.ha = 1080, .hbl = 64, .hso = 26, .hspw = 2,
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.va = 2248, .vbl = 64, .vso = 56, .vspw = 4,
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.phsync = '-', .pvsync = '-',
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.x_mm = 74, .y_mm = 131,
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},
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},
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.orientation = LB_FB_ORIENTATION_NORMAL,
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.init = {
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PANEL_DCS(0xFE, 0x00, 0x15, 0x80),
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PANEL_DCS(0xc2, 0x08, 0x15, 0x80),
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PANEL_DCS(0x35, 0x00, 0x15, 0x80),
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PANEL_DCS(0x51, 0xff, 0x15, 0x80),
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PANEL_DCS(0x11, 0x00, 0x05, 0x80),
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PANEL_DELAY(150),
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PANEL_DCS(0x29, 0x00, 0x05, 0x80),
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PANEL_DELAY(50),
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PANEL_END,
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},
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};
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@ -15,6 +15,7 @@ config TROGDOR_HAS_BRIDGE_BACKLIGHT
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config TROGDOR_HAS_MIPI_PANEL
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bool
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default n
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select MIPI_PANEL_VIS_RM69299
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config TROGDOR_HAS_FINGERPRINT
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bool
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@ -15,7 +15,6 @@ romstage-y += boardid.c
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romstage-y += chromeos.c
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ramstage-y += mainboard.c
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ramstage-y += panel_driver.c
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ifneq ($(CONFIG_BOARD_GOOGLE_BUBS),y)
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ramstage-y += reset.c
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endif
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@ -1,11 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootmode.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/i2c_simple.h>
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#include <device/mipi_panel.h>
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#include <drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h>
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#include <edid.h>
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#include <framebuffer_info.h>
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#include <soc/display/mipi_dsi.h>
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#include <soc/display/mdssreg.h>
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@ -64,7 +67,7 @@ static void load_qup_fw(void)
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qupv3_se_fw_load_and_init(QUPV3_1_SE5, SE_PROTOCOL_I2C, MIXED); /* Codec I2C */
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}
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static void configure_display(void)
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static void power_on_bridge(void)
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{
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printk(BIOS_INFO, "%s: Bridge gpio init\n", __func__);
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@ -75,25 +78,38 @@ static void configure_display(void)
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gpio_output(GPIO_EN_PP3300_DX_EDP, 1);
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}
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static enum cb_err display_init(struct edid *edid, const struct panel_data *pinfo)
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static struct panel_serializable_data *get_mipi_panel(void)
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{
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uint32_t dsi_bpp = 24;
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uint32_t lanes = pinfo ? pinfo->lanes : 4;
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const char *cbfs_filename = "panel-VIS_RM69299";
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if (mdss_dsi_config(edid, lanes, dsi_bpp))
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return CB_ERR;
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if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) {
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if (mdss_dsi_panel_initialize(pinfo))
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return CB_ERR;
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} else {
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sn65dsi86_bridge_configure(BRIDGE_BUS, BRIDGE_CHIP, edid, lanes, dsi_bpp);
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struct panel_serializable_data *panel = cbfs_map(cbfs_filename, NULL);
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if (!panel) {
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printk(BIOS_ERR, "Could not find panel data for %s!\n", cbfs_filename);
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return NULL;
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}
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if (CONFIG(TROGDOR_HAS_BRIDGE_BACKLIGHT))
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sn65dsi86_backlight_enable(BRIDGE_BUS, BRIDGE_CHIP);
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return panel;
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}
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mdp_dsi_video_config(edid);
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mdss_dsi_video_mode_config(edid, dsi_bpp);
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static enum cb_err display_init(struct panel_serializable_data *panel)
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{
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uint32_t dsi_bpp = 24;
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uint32_t lanes = 4;
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if (mdss_dsi_config(&panel->edid, lanes, dsi_bpp))
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return CB_ERR;
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if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) {
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if (mdss_dsi_panel_initialize(panel->init))
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return CB_ERR;
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} else {
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sn65dsi86_bridge_configure(BRIDGE_BUS, BRIDGE_CHIP, &panel->edid,
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lanes, dsi_bpp);
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if (CONFIG(TROGDOR_HAS_BRIDGE_BACKLIGHT))
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sn65dsi86_backlight_enable(BRIDGE_BUS, BRIDGE_CHIP);
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}
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mdp_dsi_video_config(&panel->edid);
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mdss_dsi_video_mode_config(&panel->edid, dsi_bpp);
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mdp_dsi_video_on();
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return CB_SUCCESS;
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@ -101,28 +117,37 @@ static enum cb_err display_init(struct edid *edid, const struct panel_data *pinf
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static void display_startup(void)
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{
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static struct edid ed;
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enum dp_pll_clk_src ref_clk = SN65_SEL_19MHZ;
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const struct panel_data *pinfo = NULL;
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struct panel_serializable_data *panel = NULL;
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if (display_init_required()) {
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if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) {
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pinfo = get_panel_config(&ed);
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} else {
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i2c_init(QUPV3_0_SE2, I2C_SPEED_FAST); /* EDP Bridge I2C */
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configure_display();
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mdelay(250); /* Delay for the panel to be up */
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sn65dsi86_bridge_init(BRIDGE_BUS, BRIDGE_CHIP, ref_clk);
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if (sn65dsi86_bridge_read_edid(BRIDGE_BUS, BRIDGE_CHIP, &ed) < 0)
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return;
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}
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printk(BIOS_INFO, "display init!\n");
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if (display_init(&ed, pinfo) == CB_SUCCESS)
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fb_new_framebuffer_info_from_edid(&ed, (uintptr_t)0);
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} else
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if (!display_init_required()) {
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printk(BIOS_INFO, "Skipping display init.\n");
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return;
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}
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if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) {
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panel = get_mipi_panel();
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if (!panel)
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return;
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} else {
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enum dp_pll_clk_src ref_clk = SN65_SEL_19MHZ;
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static struct panel_serializable_data edp_panel = {
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.orientation = LB_FB_ORIENTATION_NORMAL,
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};
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i2c_init(QUPV3_0_SE2, I2C_SPEED_FAST); /* EDP Bridge I2C */
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power_on_bridge();
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mdelay(250); /* Delay for the panel to be up */
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sn65dsi86_bridge_init(BRIDGE_BUS, BRIDGE_CHIP, ref_clk);
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if (sn65dsi86_bridge_read_edid(BRIDGE_BUS, BRIDGE_CHIP, &edp_panel.edid) < 0)
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return;
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panel = &edp_panel;
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}
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printk(BIOS_INFO, "display init!\n");
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edid_set_framebuffer_bits_per_pixel(&panel->edid, 32, 0);
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if (display_init(panel) == CB_SUCCESS) {
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struct fb_info *info = fb_new_framebuffer_info_from_edid(&panel->edid, 0);
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fb_set_orientation(info, panel->orientation);
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}
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}
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static void mainboard_init(struct device *dev)
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@ -1,45 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <edid.h>
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#include <string.h>
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#include <types.h>
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#include <soc/display/mipi_dsi.h>
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#include <soc/display/panel.h>
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struct mipi_dsi_cmd visionox_init_cmds[] = {
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{{0xFE, 0x00, 0x15, 0x80}, 0x4, 0},
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{{0xc2, 0x08, 0x15, 0x80}, 0x4, 0},
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{{0x35, 0x00, 0x15, 0x80}, 0x4, 0},
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{{0x51, 0xff, 0x15, 0x80}, 0x4, 0},
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{{0x11, 0x00, 0x05, 0x80}, 0x4, 150000},
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{{0x29, 0x00, 0x05, 0x80}, 0x4, 50000},
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};
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static const struct edid visionox_edid = {
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.ascii_string = "RM69299",
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.manufacturer_name = "RM",
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.panel_bits_per_color = 8,
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.panel_bits_per_pixel = 24,
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.mode = {
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.pixel_clock = 158695,
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.lvds_dual_channel = 0,
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.refresh = 60,
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.ha = 1080, .hbl = 64, .hso = 26, .hspw = 2,
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.va = 2248, .vbl = 64, .vso = 56, .vspw = 4,
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.phsync = '-', .pvsync = '-',
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.x_mm = 74, .y_mm = 131,
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},
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};
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const struct panel_data panel_info = {
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.lanes = 4,
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.init_cmd = visionox_init_cmds,
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.init_cmd_count = 6,
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};
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const struct panel_data *get_panel_config(struct edid *edid)
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{
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memcpy(edid, &visionox_edid, sizeof(struct edid));
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edid_set_framebuffer_bits_per_pixel(edid, 32, 0);
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return &panel_info;
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}
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@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mipi_panel.h>
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#include <device/mmio.h>
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#include <console/console.h>
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#include <assert.h>
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@ -9,7 +10,6 @@
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#include <types.h>
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#include <string.h>
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#include <soc/display/mipi_dsi.h>
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#include <soc/display/panel.h>
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#include <soc/display/mdssreg.h>
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#include <soc/display/dsi_phy.h>
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@ -30,7 +30,7 @@
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#define HS_TX_TO 0xEA60
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#define TIMER_RESOLUTION 0x4
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#define DSI_PAYLOAD_BYTE_BOUND 8
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#define DSI_PAYLOAD_BYTE_BOUND 256
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#define DSI_PAYLOAD_SIZE_ALIGN 4
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#define DSI_CMD_DMA_TPG_EN BIT(1)
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#define DSI_TPG_DMA_FIFO_MODE BIT(2)
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@ -210,57 +210,55 @@ static int mdss_dsi_cmd_dma_trigger_for_panel(void)
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return status;
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}
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static int mdss_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count)
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static cb_err_t mdss_dsi_send_init_cmd(enum panel_init_cmd cmd, const u8 *body, u8 len)
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{
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struct mipi_dsi_cmd *cm;
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uint8_t *pload = _dma_coherent;
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uint32_t size;
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cb_err_t ret = CB_SUCCESS;
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int data = 0;
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int ret = 0;
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uint32_t *bp = NULL;
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cm = cmds;
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/* This implementation only supports DCS commands (I think?). */
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assert(cmd == PANEL_CMD_DCS);
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for (int i = 0; i < count; i++) {
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/* The payload size has to be a multiple of 4 */
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size = ALIGN_UP(cm->size, DSI_PAYLOAD_SIZE_ALIGN);
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assert(size < DSI_PAYLOAD_BYTE_BOUND);
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memcpy(pload, (cm[i].payload), size);
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/* The payload size has to be a multiple of 4 */
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memcpy(pload, body, len);
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size = ALIGN_UP(len, DSI_PAYLOAD_SIZE_ALIGN);
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memset(pload + len, 0xff, size - len);
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assert(size < DSI_PAYLOAD_BYTE_BOUND);
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bp = (uint32_t *)pload;
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bp = (uint32_t *)pload;
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/* Enable custom pattern stored in TPG DMA FIFO */
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data = DSI_CMD_DMA_PATTERN_SEL;
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/* Enable custom pattern stored in TPG DMA FIFO */
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data = DSI_CMD_DMA_PATTERN_SEL;
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/* select CMD_DMA_FIFO_MODE to 1 */
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data |= DSI_TPG_DMA_FIFO_MODE;
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data |= DSI_CMD_DMA_TPG_EN;
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/* select CMD_DMA_FIFO_MODE to 1 */
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data |= DSI_TPG_DMA_FIFO_MODE;
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data |= DSI_CMD_DMA_TPG_EN;
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write32(&dsi0->test_pattern_gen_ctrl, data);
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for (int j = 0; j < size; j += 4) {
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write32(&dsi0->test_pattern_gen_cmd_dma_init_val, *bp);
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bp++;
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}
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if ((size % 8) != 0)
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write32(&dsi0->test_pattern_gen_cmd_dma_init_val, 0x0);
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write32(&dsi0->dma_cmd_length, size);
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write32(&dsi0->cmd_mode_dma_sw_trigger, 0x1);
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ret += mdss_dsi_cmd_dma_trigger_for_panel();
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/* Reset the DMA TPG FIFO */
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write32(&dsi0->tpg_dma_fifo_reset, 0x1);
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write32(&dsi0->tpg_dma_fifo_reset, 0x0);
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/* Disable CMD_DMA_TPG */
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write32(&dsi0->test_pattern_gen_ctrl, 0x0);
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if (cm[i].delay_us)
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udelay(cm[i].delay_us);
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else
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udelay(80);
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write32(&dsi0->test_pattern_gen_ctrl, data);
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for (int j = 0; j < size; j += 4) {
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write32(&dsi0->test_pattern_gen_cmd_dma_init_val, *bp);
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bp++;
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}
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if ((size % 8) != 0)
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write32(&dsi0->test_pattern_gen_cmd_dma_init_val, 0x0);
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write32(&dsi0->dma_cmd_length, size);
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write32(&dsi0->cmd_mode_dma_sw_trigger, 0x1);
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if (mdss_dsi_cmd_dma_trigger_for_panel())
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ret = CB_ERR;
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/* Reset the DMA TPG FIFO */
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write32(&dsi0->tpg_dma_fifo_reset, 0x1);
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write32(&dsi0->tpg_dma_fifo_reset, 0x0);
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/* Disable CMD_DMA_TPG */
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write32(&dsi0->test_pattern_gen_ctrl, 0x0);
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udelay(80);
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return ret;
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}
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@ -274,22 +272,19 @@ static void mdss_dsi_clear_intr(void)
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write32(&dsi0->err_int_mask0, 0x13FF3BFF);
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}
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int mdss_dsi_panel_initialize(const struct panel_data *pinfo)
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cb_err_t mdss_dsi_panel_initialize(const u8 *init_cmds)
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{
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int status = 0;
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uint32_t ctrl_mode = 0;
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struct mipi_dsi_cmd *cmds;
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assert((pinfo != NULL) && (pinfo->init_cmd != NULL));
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cmds = pinfo->init_cmd;
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assert(init_cmds != NULL);
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ctrl_mode = read32(&dsi0->ctrl);
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/* Enable command mode before sending the commands */
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write32(&dsi0->ctrl, ctrl_mode | 0x04);
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status = mdss_dsi_cmds_tx(cmds, pinfo->init_cmd_count);
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cb_err_t ret = mipi_panel_parse_init_commands(init_cmds, mdss_dsi_send_init_cmd);
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write32(&dsi0->ctrl, ctrl_mode);
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mdss_dsi_clear_intr();
|
||||
|
||||
return status;
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@
|
|||
#ifndef _SOC_DISPLAY_MIPI_DSI_H_
|
||||
#define _SOC_DISPLAY_MIPI_DSI_H_
|
||||
|
||||
#include <soc/display/panel.h>
|
||||
/**********************************************************
|
||||
DSI register configuration options
|
||||
**********************************************************/
|
||||
|
|
@ -15,12 +14,6 @@
|
|||
#define DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2
|
||||
#define DSI_VIDEO_DST_FORMAT_RGB888 3
|
||||
|
||||
struct mipi_dsi_cmd {
|
||||
char payload[4];
|
||||
uint32_t size;
|
||||
int delay_us;
|
||||
};
|
||||
|
||||
enum {
|
||||
DSI_VIDEO_MODE,
|
||||
DSI_CMD_MODE,
|
||||
|
|
@ -29,6 +22,6 @@ enum {
|
|||
enum cb_err mdss_dsi_config(struct edid *edid, uint32_t num_of_lanes, uint32_t bpp);
|
||||
void mdss_dsi_clock_config(void);
|
||||
void mdss_dsi_video_mode_config(struct edid *edid, uint32_t bpp);
|
||||
int mdss_dsi_panel_initialize(const struct panel_data *pinfo);
|
||||
cb_err_t mdss_dsi_panel_initialize(const u8 *init_cmds);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,17 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _PANEL_H_
|
||||
#define _PANEL_H_
|
||||
|
||||
#include <types.h>
|
||||
|
||||
struct panel_data {
|
||||
uint8_t lanes;
|
||||
struct mipi_dsi_cmd *init_cmd;
|
||||
uint32_t init_cmd_count;
|
||||
};
|
||||
|
||||
void panel_power_on(void);
|
||||
const struct panel_data *get_panel_config(struct edid *edid);
|
||||
|
||||
#endif /*_PANEL_H_ */
|
||||
Loading…
Reference in New Issue