sb/intel/i82801ix: Use the common ACPI pirq generator
For this to work the northbridge and lpc bridge device need acpi_name functions. TESTED on Thinkpad X200, a valid PIRQ routing in SSDT in /sys/firmware/acpi/tables/SSDT Change-Id: I62e520f53fa3f928a8e6f3b3cf33af2acdd53ed9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This is board specific information: IRQ routing for the
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* gm45
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*/
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// PCI Interrupt Routing
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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// PCIe Graphics 0:1.0
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Package() { 0x0001ffff, 0, 0, 16 },
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, 0, 16 },
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// Onboard GbE
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Package() { 0x0019ffff, 0, 0, 16 },
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// USB and EHCI 0:1a.x
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Package() { 0x001affff, 0, 0, 16 },
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Package() { 0x001affff, 1, 0, 17 },
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Package() { 0x001affff, 2, 0, 18 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, 0, 16 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, 0, 16 },
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Package() { 0x001cffff, 1, 0, 17 },
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Package() { 0x001cffff, 2, 0, 18 },
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Package() { 0x001cffff, 3, 0, 19 },
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// USB and EHCI 0:1d.x
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Package() { 0x001dffff, 0, 0, 16 },
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Package() { 0x001dffff, 1, 0, 17 },
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Package() { 0x001dffff, 2, 0, 18 },
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// LPC bridge sub devices 0:1f.x
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Package() { 0x001fffff, 1, 0, 17 },
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Package() { 0x001fffff, 2, 0, 18 }
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})
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} Else {
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Return (Package() {
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// PCIe Graphics 0:1.0
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Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// Onboard GbE
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Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// USB and EHCI 0:1a.x
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Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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// USB and EHCI 0:1d.x
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Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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// LPC bridge sub devices 0:1f.x
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }
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})
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}
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}
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@ -1,80 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This is board specific information: IRQ routing for the
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* gm45
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*/
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// PCI Interrupt Routing
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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// PCIe Graphics 0:1.0
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Package() { 0x0001ffff, 0, 0, 16 },
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, 0, 16 },
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// Onboard GbE
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Package() { 0x0019ffff, 0, 0, 16 },
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// USB and EHCI 0:1a.x
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Package() { 0x001affff, 0, 0, 16 },
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Package() { 0x001affff, 1, 0, 17 },
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Package() { 0x001affff, 2, 0, 18 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, 0, 16 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, 0, 16 },
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Package() { 0x001cffff, 1, 0, 17 },
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Package() { 0x001cffff, 2, 0, 18 },
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Package() { 0x001cffff, 3, 0, 19 },
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// USB and EHCI 0:1d.x
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Package() { 0x001dffff, 0, 0, 16 },
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Package() { 0x001dffff, 1, 0, 17 },
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Package() { 0x001dffff, 2, 0, 18 },
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// LPC bridge sub devices 0:1f.x
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Package() { 0x001fffff, 1, 0, 17 },
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Package() { 0x001fffff, 2, 0, 18 }
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})
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} Else {
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Return (Package() {
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// PCIe Graphics 0:1.0
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Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// Onboard GbE
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Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// USB and EHCI 0:1a.x
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Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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// USB and EHCI 0:1d.x
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Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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// LPC bridge sub devices 0:1f.x
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }
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})
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}
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}
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@ -1,80 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This is board specific information: IRQ routing for the
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* gm45
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*/
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// PCI Interrupt Routing
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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// PCIe Graphics 0:1.0
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Package() { 0x0001ffff, 0, 0, 16 },
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, 0, 16 },
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// USB and EHCI 0:1a.x
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Package() { 0x001affff, 0, 0, 16 },
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Package() { 0x001affff, 1, 0, 17 },
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Package() { 0x001affff, 2, 0, 18 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, 0, 16 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, 0, 16 },
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// USB and EHCI 0:1d.x
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Package() { 0x001dffff, 0, 0, 16 },
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Package() { 0x001dffff, 1, 0, 17 },
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Package() { 0x001dffff, 2, 0, 18 },
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// FIXME
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// CardBus/IEEE1394 0:1e.2, 0:1e.3
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// Package() { 0x001effff, 0, 0, 22 },
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// Package() { 0x001effff, 1, 0, 20 },
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// LPC device 0:1f.0
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Package() { 0x001fffff, 0, 0, 16 },
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Package() { 0x001fffff, 1, 0, 17 },
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Package() { 0x001fffff, 2, 0, 18 }
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})
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} Else {
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Return (Package() {
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// PCIe Graphics 0:1.0
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Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// USB and EHCI 0:1a.x
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Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// USB and EHCI 0:1d.x
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Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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// FIXME
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// CardBus/IEEE1394 0:1e.2, 0:1e.3
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// Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
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// Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
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// LPC device 0:1f.0
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Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }
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})
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}
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}
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@ -228,6 +228,3 @@ Method (_CRS, 0, Serialized)
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Return (MCRS)
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}
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/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
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#include "acpi/gm45_pci_irqs.asl"
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@ -191,6 +191,22 @@ static void mch_domain_init(struct device *dev)
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pci_write_config32(dev, PCI_COMMAND, reg32);
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}
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static const char *northbridge_acpi_name(const struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0)
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return NULL;
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switch (dev->path.pci.devfn) {
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case PCI_DEVFN(0, 0):
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return "MCHC";
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}
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return NULL;
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = mch_domain_read_resources,
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.set_resources = mch_domain_set_resources,
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.scan_bus = pci_domain_scan_bus,
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.write_acpi_tables = northbridge_write_acpi_tables,
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.acpi_fill_ssdt_generator = generate_cpu_entries,
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.acpi_name = northbridge_acpi_name,
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};
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@ -18,6 +18,7 @@ config SOUTHBRIDGE_INTEL_I82801IX
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bool
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select SOUTHBRIDGE_INTEL_COMMON
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
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select IOAPIC
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select HAVE_USBDEBUG
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select HAVE_HARD_RESET
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#include "nvs.h"
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#include <southbridge/intel/common/pciehp.h>
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#include <drivers/intel/gma/i915.h>
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#include <southbridge/intel/common/acpi_pirq_gen.h>
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#define NMI_OFF 0
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}
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}
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static const char *lpc_acpi_name(const struct device *dev)
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{
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return "LPCB";
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}
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static void southbridge_fill_ssdt(struct device *device)
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{
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struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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config_t *chip = dev->chip_info;
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intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
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intel_acpi_gen_def_acpi_pirq(device);
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}
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static struct pci_operations pci_ops = {
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.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
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.write_acpi_tables = acpi_write_hpet,
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.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
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.acpi_name = lpc_acpi_name,
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.init = lpc_init,
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.scan_bus = scan_lpc_bus,
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.ops_pci = &pci_ops,
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