diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index f2f7e0e103..47017393d3 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -21,6 +21,7 @@ config VARIANT_DIR default "mc_apl4" if BOARD_SIEMENS_MC_APL4 default "mc_apl5" if BOARD_SIEMENS_MC_APL5 default "mc_apl6" if BOARD_SIEMENS_MC_APL6 + default "mc_apl7" if BOARD_SIEMENS_MC_APL7 config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" @@ -32,6 +33,7 @@ config MAINBOARD_PART_NUMBER default "MC APL4" if BOARD_SIEMENS_MC_APL4 default "MC APL5" if BOARD_SIEMENS_MC_APL5 default "MC APL6" if BOARD_SIEMENS_MC_APL6 + default "MC APL7" if BOARD_SIEMENS_MC_APL7 config UART_FOR_CONSOLE default 2 diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name index 225dd19d44..9c9ff27760 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig.name +++ b/src/mainboard/siemens/mc_apl1/Kconfig.name @@ -23,3 +23,7 @@ config BOARD_SIEMENS_MC_APL5 config BOARD_SIEMENS_MC_APL6 bool "-> MC APL6" select BOARD_SIEMENS_BASEBOARD_MC_APL1 + +config BOARD_SIEMENS_MC_APL7 + bool "-> MC APL7" + select BOARD_SIEMENS_BASEBOARD_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/Kconfig new file mode 100644 index 0000000000..a4a958919c --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/Kconfig @@ -0,0 +1,32 @@ + +if BOARD_SIEMENS_MC_APL7 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select DRIVER_INTEL_I210 + select SOC_INTEL_SET_MIN_CLOCK_RATIO + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select TPM_ON_FAST_SPI + select DRIVERS_I2C_PTN3460 + select TPM_MEASURED_BOOT + select HAS_RECOVERY_MRC_CACHE + +config UART_FOR_CONSOLE + default 1 + +config CBFS_SIZE + default 0xb4e000 + +config VBOOT + select VBOOT_VBNV_FLASH + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_apl_vboot.fmd" + +endif # BOARD_SIEMENS_MC_APL7 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/Makefile.inc new file mode 100644 index 0000000000..e26339c548 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c +ramstage-y += lcd_panel.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb new file mode 100644 index 0000000000..58791f3f10 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb @@ -0,0 +1,115 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "sci_irq" = "SCIS_IRQ10" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # 0:HS400(Default), 1:HS200, 2:DDR50 + register "emmc_host_max_speed" = "1" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen - Display + device pci 03.0 off end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE + device pci 11.0 on end # - ISH + device pci 12.0 on # - SATA + register "DisableSataSalpSupport" = "1" + end + device pci 13.0 on # - RP 2 - PCIe A 0 + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[2]" = "0" + end + device pci 13.1 on # - RP 3 - PCIe A 1 + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[3]" = "0" + end + device pci 13.2 on # - RP 4 - PCIe-A 2 + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[4]" = "0" + end + device pci 13.3 on # - RP 5 - PCIe-A 3 + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[5]" = "0" + end + device pci 14.0 on # - RP 0 - PCIe-B 0 + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[0]" = "0" + end + device pci 14.1 on # - RP 1 - PCIe-B 1 + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[1]" = "0" + end + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on # - I2C 7 + # Enable external display bridge (eDP to LVDS) + chip drivers/i2c/ptn3460 + device i2c 0x60 on end # PTN3460 DP2LVDS Bridge + end + end + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 off end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 off end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1d.0 off end # - UFS + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/gpio.c new file mode 100644 index 0000000000..2d7bea4341 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/gpio.c @@ -0,0 +1,380 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* + * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' + * table found in EDS vol 1, but some pins aren't grouped functionally in + * the table so those were moved for more logical grouping. + */ +static const struct pad_config gpio_table[] = { + /* Southwest Community */ + + /* PCIE_WAKE[0:3]_N - unused */ + PAD_CFG_GPI(GPIO_205, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_206, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_207, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_208, UP_20K, DEEP), + + /* EMMC interface. */ + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ + PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ + PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ + PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ + PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ + PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ + PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ + PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ + PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + + /* SDIO - unused */ + PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_167, DN_20K, DEEP), + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), + PAD_CFG_GPI(GPIO_169, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_170, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_171, DN_20K, DEEP), + + /* SDCARD */ + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ + PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */ + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ + /* + * SDCARD_CLK_FB - APL EDS Vol1 remarks: + * This is not a physical GPIO that can be used. This Signal is not Ball + * out on the SoC, only the buffer exists. + */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_186, UP_20K, DEEP, NF1), /* SDCARD_WP_1V8 */ + PAD_CFG_TERM_GPO(GPIO_183, 1, UP_20K, DEEP), /* SD_PWR_EN_1V8 */ + + /* West Community */ + + PAD_CFG_GPI(GPIO_124, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_125, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_126, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_127, DN_20K, DEEP), /* unused */ + + PAD_CFG_NF(GPIO_128, NONE, DEEP, NF1), /* provided LPSS_I2C2_SDA */ + PAD_CFG_NF(GPIO_129, NONE, DEEP, NF1), /* provided LPSS_I2C2_SCL */ + + PAD_CFG_GPI(GPIO_130, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_131, DN_20K, DEEP), /* unused */ + + PAD_CFG_NF(GPIO_132, NONE, DEEP, NF1), /* provided LPSS_I2C4_SDA */ + PAD_CFG_NF(GPIO_133, NONE, DEEP, NF1), /* provided LPSS_I2C4_SCL */ + + /* + * Hint for USB enable power: some GPIOs are open drain outputs, + * to drive high -> Bit GPIO_TX_DIS has to be set in combination with PU + * PAD_CFG_GPO macro does not work. Refer to APL EDS Vol 4. + */ + PAD_CFG_GPI(GPIO_134, UP_20K, DEEP), /* enable USB0 power */ + PAD_CFG_GPI(GPIO_135, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* enable USB7 power */ + PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* enable USB6 power */ + PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* enable USB2 power */ + PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* enable USB1 power */ + + /* ISH_GPIO_[0:9] -- unused */ + PAD_CFG_GPI(GPIO_146, DN_20K, DEEP), /* ISH_GPIO_0 */ + PAD_CFG_GPI(GPIO_147, DN_20K, DEEP), /* ISH_GPIO_1 */ + PAD_CFG_GPI(GPIO_148, DN_20K, DEEP), /* ISH_GPIO_2 */ + PAD_CFG_GPI(GPIO_149, DN_20K, DEEP), /* ISH_GPIO_3 */ + PAD_CFG_GPI(GPIO_150, DN_20K, DEEP), /* ISH_GPIO_4 */ + PAD_CFG_GPI(GPIO_151, DN_20K, DEEP), /* ISH_GPIO_5 */ + PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* ISH_GPIO_6 */ + PAD_CFG_GPI(GPIO_153, DN_20K, DEEP), /* ISH_GPIO_7 */ + PAD_CFG_GPI(GPIO_154, DN_20K, DEEP), /* ISH_GPIO_8 */ + PAD_CFG_GPI(GPIO_155, DN_20K, DEEP), /* ISH_GPIO_9 */ + + /* PCIE_CLKREQ[0:3]_N */ + PAD_CFG_NF(GPIO_209, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_210, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_211, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_212, DN_20K, DEEP, NF1), + + /* OSC_CLK_OUT_[0:4] - unused */ + PAD_CFG_GPI(OSC_CLK_OUT_0, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_1, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_2, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_3, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP), + + /* PMU Signals */ + PAD_CFG_NF(PMU_AC_PRESENT, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), + PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), + PAD_CFG_GPI(PMU_SLP_S0_B, UP_20K, DEEP), + PAD_CFG_GPI(PMU_SLP_S3_B, UP_20K, DEEP), + PAD_CFG_GPI(PMU_SLP_S4_B, UP_20K, DEEP), + PAD_CFG_GPI(PMU_WAKE_B, DN_20K, DEEP), + PAD_CFG_GPI(SUS_STAT_B, DN_20K, DEEP), + PAD_CFG_GPI(SUSPWRDNACK, DN_20K, DEEP), + + /* Northwest Community */ + + /* DDI0 SDA and SCL - Display-Port X24 */ + PAD_CFG_NF(GPIO_187, UP_20K, DEEP, NF1), /* HV_DDI0_DDC_SDA */ + PAD_CFG_NF(GPIO_188, UP_20K, DEEP, NF1), /* HV_DDI0_DDC_SCL */ + /* DDI1 SDA and SCL - unused */ + PAD_CFG_GPI(GPIO_189, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_190, DN_20K, DEEP), + /* MIPI I2C - unused */ + PAD_CFG_GPI(GPIO_191, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_192, DN_20K, DEEP), + + /* Panel 0 control - unused */ + PAD_CFG_GPI(GPIO_193, DN_20K, DEEP), /* PNL0_VDDEN */ + PAD_CFG_GPI(GPIO_194, DN_20K, DEEP), /* PNL0_BKLTEN */ + PAD_CFG_GPI(GPIO_195, DN_20K, DEEP), /* PNL0_BKLTCTL */ + + /* Panel 1 control - unused */ + PAD_CFG_GPI(GPIO_196, DN_20K, DEEP), /* PNL1_VDDEN */ + PAD_CFG_GPI(GPIO_197, DN_20K, DEEP), /* PNL1_BKLTEN */ + PAD_CFG_GPI(GPIO_198, DN_20K, DEEP), /* PNL1_BKLTCTL */ + + /* DDI[0:1]_HPD */ + PAD_CFG_GPI(GPIO_199, UP_20K, DEEP), /* DDI1_HPD unused */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* DDI0_HDP X24 */ + + /* MDSI signals - unused */ + PAD_CFG_GPI(GPIO_201, DN_20K, DEEP), /* MDSI_A_TE */ + PAD_CFG_GPI(GPIO_202, DN_20K, DEEP), /* MDSI_C_TE */ + + /* USB overcurrent pins. */ + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), /* USB_OC0_N */ + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), /* USB_OC1_N */ + + /* PMC SPI */ + PAD_CFG_GPI(PMC_SPI_FS0, DN_20K, DEEP), /* unused */ + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* XHPD_EDP_APL */ + PAD_CFG_GPI(PMC_SPI_FS2, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(PMC_SPI_RXD, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(PMC_SPI_TXD, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), /* unused */ + + /* PMIC Signals unused signals related to an old PMIC interface. */ + PAD_CFG_NF(PMIC_PWRGOOD, DN_20K, DEEP, NF1), /* PMIC_PWRGOOD */ + PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */ + PAD_CFG_GPI(GPIO_213, UP_20K, DEEP), /* PMIC_SDWN_B */ + PAD_CFG_GPI(GPIO_214, DN_20K, DEEP), /* PMIC_BCUDISW2 */ + PAD_CFG_GPI(GPIO_215, DN_20K, DEEP), /* PMIC_BCUDISCRIT */ + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1),/* THERMTRIP_N */ + PAD_CFG_GPI(PMIC_STDBY, DN_20K, DEEP), /* PMIC_STDBY */ + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */ + PAD_CFG_GPI(PMIC_I2C_SCL, DN_20K, DEEP), /* unused */ + PAD_CFG_GPI(PMIC_I2C_SDA, DN_20K, DEEP), /* unused */ + + /* I2S1 - unused */ + PAD_CFG_GPI(GPIO_74, DN_20K, DEEP), /* I2S1_MCLK */ + PAD_CFG_GPI(GPIO_75, DN_20K, DEEP), /* I2S1_BCLK */ + PAD_CFG_GPI(GPIO_76, DN_20K, DEEP), /* I2S1_WS_SYNC */ + PAD_CFG_GPI(GPIO_77, DN_20K, DEEP), /* I2S1_SDI */ + PAD_CFG_GPI(GPIO_78, DN_20K, DEEP), /* I2S1_SDO */ + + /* DMIC or I2S4 - unused */ + PAD_CFG_GPI(GPIO_79, DN_20K, DEEP), /* AVS_M_CLK_A1 */ + PAD_CFG_GPI(GPIO_80, DN_20K, DEEP), /* AVS_M_CLK_B1 */ + PAD_CFG_GPI(GPIO_81, DN_20K, DEEP), /* AVS_M_DATA_1 */ + PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* AVS_M_CLK_AB2 */ + PAD_CFG_GPI(GPIO_83, DN_20K, DEEP), /* AVS_M_DATA_2 */ + + /* I2S2 - unused */ + PAD_CFG_GPO(GPIO_84, 0, DEEP), /* AVS_I2S2_MCLK */ + PAD_CFG_GPI(GPIO_85, DN_20K, DEEP), /* AVS_I2S2_BCLK */ + PAD_CFG_GPI(GPIO_86, DN_20K, DEEP), /* AVS_I2S2_WS_SYNC */ + PAD_CFG_GPI(GPIO_87, DN_20K, DEEP), /* AVS_I2S2_SDI */ + PAD_CFG_GPI(GPIO_88, DN_20K, DEEP), /* AVS_I2S2_SDO */ + + /* I2S3 - unused */ + PAD_CFG_GPI(GPIO_89, DN_20K, DEEP), /* AVS_I2S3_BCLK */ + PAD_CFG_GPI(GPIO_90, DN_20K, DEEP), /* AVS_I2S3_WS_SYNC */ + PAD_CFG_GPI(GPIO_91, DN_20K, DEEP), /* AVS_I2S3_SDI */ + PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* AVS_I2S3_SDO */ + + /* Fast SPI for mainboard Flash and TPM on mainboard. */ + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), /* FST_SPI_CS0_B */ + PAD_CFG_GPI(GPIO_98, DN_20K, DEEP), /* FST_SPI_CS1_B - unused */ + PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1),/* FST_SPI_MISO_IO1 */ + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1),/* FST_IO2 - MEM_CONFIG0 */ + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1),/* FST_IO3 - MEM_CONFIG1 */ + PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1),/* FST_SPI_CLK */ + /* FST_SPI_CLK_FB - Pad not bonded, default register value is the same + * as here. Refer to Intel Doc APL EDS Vol 1 */ + PAD_CFG_NF(FST_SPI_CLK_FB, NONE, DEEP, NF1), + + /* SIO_SPI_0 for F-module on mainboard */ + PAD_CFG_NF(GPIO_104, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_105, UP_20K, DEEP, NF1), + /* GPIO_106 configured as XCS for TPM */ + PAD_CFG_NF(GPIO_106, UP_20K, DEEP, NF3), + PAD_CFG_NF(GPIO_109, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_110, UP_20K, DEEP, NF1), + + /* SIO_SPI_1 -- unused */ + PAD_CFG_GPI(GPIO_111, DN_20K, DEEP), /* GP_SSP_1_CLK */ + PAD_CFG_GPI(GPIO_112, DN_20K, DEEP), /* GP_SSP_1_FS0 */ + PAD_CFG_GPI(GPIO_113, DN_20K, DEEP), /* GP_SSP_1_FS1 */ + PAD_CFG_GPI(GPIO_116, DN_20K, DEEP), /* GP_SSP_1_RXD */ + PAD_CFG_GPI(GPIO_117, DN_20K, DEEP), /* GP_SSP_1_TXD */ + + /* SIO_SPI_2 -- unused */ + PAD_CFG_GPI(GPIO_118, UP_20K, DEEP), /* GP_SSP_2_CLK */ + PAD_CFG_GPI(GPIO_119, DN_20K, DEEP), /* GP_SSP_2_FS0 */ + PAD_CFG_GPI(GPIO_120, DN_20K, DEEP), /* GP_SSP_2_FS1 */ + PAD_CFG_GPI(GPIO_121, DN_20K, DEEP), /* GP_SSP_2_FS2 */ + PAD_CFG_GPI(GPIO_122, DN_20K, DEEP), /* GP_SSP_2_RXD */ + PAD_CFG_GPI(GPIO_123, DN_20K, DEEP), /* GP_SSP_2_TXD */ + + /* North Community */ + + PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), + /* GPIO_1 in early_gpio_table */ + PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), + /* GPIO_3,4 in early_gpio_table */ + PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */ + PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */ + PAD_CFG_GPO(GPIO_7, 0, DEEP), + PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_9, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_11, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_12, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_13, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_14, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_15, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_16, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_17, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_18, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_19, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_20, DN_20K, DEEP), + PAD_CFG_GPO(GPIO_21, 0, DEEP), /* activate SMARC Ethernetmac 2 */ + PAD_CFG_GPO(GPIO_22, 0, DEEP), /* activate SMARC Ethernetmac 1 */ + PAD_CFG_GPI(GPIO_23, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_24, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_25, DN_20K, DEEP), /* pin open */ + PAD_CFG_NF(GPIO_26, UP_20K, DEEP, NF5), /* SATA_LEDN */ + PAD_CFG_GPI(GPIO_27, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPO(GPIO_28, 1, DEEP), /* disable SMARC HDMI */ + PAD_CFG_GPO(GPIO_29, 0, DEEP), + PAD_CFG_GPI(GPIO_30, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_31, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_32, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_33, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_34, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_35, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_36, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_37, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_38, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* pin open */ + + /* LPSS_UART[0:2] */ + PAD_CFG_GPI(GPIO_41, DN_20K, DEEP), /* pin open */ + /* GPIO_42/43 are in early_gpio_table */ + PAD_CFG_GPI(GPIO_44, DN_20K, DEEP), /* LPSS_UART1_RTS - unused */ + PAD_CFG_GPI(GPIO_45, DN_20K, DEEP), /* LPSS_UART1_CTS - unused */ + /* GPIO_46/47 are in early_gpio_table */ + PAD_CFG_GPI(GPIO_48, DN_20K, DEEP), /* LPSS_UART2_RTS - unused */ + PAD_CFG_GPI(GPIO_49, DN_20K, DEEP), /* LPSS_UART2_CTS - unused */ + + /* Camera interface -- completely unused. */ + PAD_CFG_GPI(GPIO_62, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_63, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_64, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_65, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_66, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPI(GPIO_67, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPO(GPIO_68, 0, DEEP), /* APL7 Testpoint P403 */ + PAD_CFG_GPO(GPIO_69, 0, DEEP), /* APL7 Testpoint P404 */ + PAD_CFG_GPI(GPIO_70, DN_20K, DEEP), /* pin open */ + PAD_CFG_GPO(GPIO_71, 1, DEEP), /* XCHC_UPD_REQ */ + PAD_CFG_GPO(GPIO_72, 0, DEEP), /* APL7 Testpoint P402 */ + PAD_CFG_GPI(GPIO_73, DN_20K, DEEP), /* pin open */ + + /* no TAP controller pins available on SMARC of APL7 */ + PAD_CFG_NF(TCK, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(TRST_B, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(TMS, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(TDI, DN_20K, DEEP, NF1), /* pin open */ + + PAD_CFG_NF(CX_PMODE, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(CX_PREQ_B, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(JTAGX, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(CX_PRDY_B, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(TDO, DN_20K, DEEP, NF1), /* pin open */ + + /* GPIO_[216:219] described into EDS Vol1. */ + PAD_CFG_GPO(CNV_BRI_DT, 0, DEEP), /* Disable eDP to LVDS bridge */ + PAD_CFG_GPI(CNV_BRI_RSP, UP_20K, DEEP), + PAD_CFG_GPI(CNV_RGI_DT, DN_20K, DEEP), /* pin open */ + + /* Writing to following GPIO registers leads to 0xFFFF FFFF in CFG0/1 */ + PAD_CFG_NF(CNV_RGI_RSP, DN_20K, DEEP, NF1), /* pin open */ + + /* Serial Voltage Identification */ + PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1), /* SVID0_ALERT_B */ + PAD_CFG_NF(SVID0_DATA, UP_20K, DEEP, NF1), /* SVID0_DATA */ + PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ + + /* Southwest Community */ + + /* Multiplexed I2C7 */ + PAD_CFG_NF(SMB_ALERTB, UP_20K, DEEP, NF2), + PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF2), + PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF2), + + /* get LPC Bus early working */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NONE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), + + /* North Community */ + PAD_CFG_GPO(GPIO_1, 1, DEEP), /* XPCIE_A_RST */ + PAD_CFG_GPO(GPIO_3, 1, DEEP), /* XPCIE_B_RST */ + PAD_CFG_GPO(GPIO_4, 1, DEEP), /* XPCIE_C_RST */ + + /* UARTs for early coreboot output */ + PAD_CFG_NF(GPIO_42, UP_20K, DEEP, NF1), /* LPSS_UART1_RXD */ + PAD_CFG_NF(GPIO_43, UP_20K, DEEP, NF1), /* LPSS_UART1_TXD */ + PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), /* LPSS_UART2_TXD */ + + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1),/* 32,78 kHz used on SMARC */ +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c new file mode 100644 index 0000000000..c1dc0bd239 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +/** \brief This function provides EDID data to the driver for DP2LVDS Bridge (PTN3460) + * @param edid_data pointer to EDID data in driver +*/ +enum cb_err mb_get_edid(uint8_t edid_data[0x80]) +{ + const char *hwi_block = "hwinfo.hex"; + + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return CB_ERR; + } + + /* Get EDID data from hwinfo block */ + if (hwilib_get_field(Edid, edid_data, PTN_EDID_LEN) != PTN_EDID_LEN) { + printk(BIOS_ERR, "LCD: No EDID data available in %s\n", hwi_block); + return CB_ERR; + } + return CB_SUCCESS; +} + +/** \brief This function provides EDID block [0..6] to the driver for DP2LVDS Bridge (PTN3460) + * which has to be used. +*/ +uint8_t mb_select_edid_table(void) +{ + return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */ +} + +/** \brief Function to enable mainboard to adjust the config data of PTN3460. + * @param *cfg_ptr Pointer to the PTN config structure to modify. + * @return -1 on error; PTN_CFG_MODIFIED if data was modified and needs to be updated. +*/ +int mb_adjust_cfg(struct ptn_3460_config *cfg) +{ + const char *hwi_block = "hwinfo.hex"; + uint8_t disp_con = 0, color_depth = 0; + + if (hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); + return -1; + } + + if (hwilib_get_field(PF_DisplCon, &disp_con, sizeof(disp_con)) != sizeof(disp_con)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return -1; + } + if (hwilib_get_field(PF_Color_Depth, &color_depth, + sizeof(color_depth)) != sizeof(color_depth)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", hwi_block); + return -1; + } + /* Set up configuration data according to the hwinfo block we got. */ + cfg->dp_interface_ctrl = 0x00; + /* Use odd-bus for clock distribution only. */ + cfg->lvds_interface_ctrl1 = 0x01; + if (disp_con == PF_DISPLCON_LVDS_DUAL) { + /* Turn on dual LVDS lane and clock. */ + cfg->lvds_interface_ctrl1 |= 0x0b; + } + if (color_depth == PF_COLOR_DEPTH_6BIT) { + /* Use 18 bits per pixel. */ + cfg->lvds_interface_ctrl1 |= 0x20; + } + /* No clock spreading, 300 mV LVDS swing. */ + cfg->lvds_interface_ctrl2 = 0x03; + /* Swap LVDS lanes (N vs. P). */ + cfg->lvds_interface_ctrl3 = 0x04; + /* Delay T2 (VDD to LVDS active) by 16 ms. */ + cfg->t2_delay = 1; + /* 500 ms from LVDS to backlight active. */ + cfg->t3_timing = 10; + /* 1 second re-power delay. */ + cfg->t12_timing = 20; + /* 150 ms backlight off to LVDS inactive. */ + cfg->t4_timing = 3; + /* Delay T5 (LVDS to VDD inactive) by 16 ms. */ + cfg->t5_delay = 1; + /* Enable backlight control. */ + cfg->backlight_ctrl = 0; + + return PTN_CFG_MODIFIED; +} diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/memory.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/memory.c new file mode 100644 index 0000000000..80d6c8ef21 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/memory.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +const struct lpddr4_swizzle_cfg mc_apl7_lpddr4_swizzle = { + /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ + .phys[LP4_PHYS_CH0A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 0, 1, 5, 3, 4, 7, 6, 2 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 11, 15, 14, 9, 8, 12, 13, 10 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 16, 22, 23, 21, 19, 17, 18, 20 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 30, 26, 31, 25, 24, 27, 28, 29 }, + }, + .phys[LP4_PHYS_CH0B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 7, 3, 2, 1, 4, 0, 6, 5 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 14, 8, 9, 15, 10, 13, 12, 11 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 23, 21, 20, 16, 19, 17, 18, 22 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 24, 25, 26, 28, 29, 31, 30, 27 }, + }, + .phys[LP4_PHYS_CH1A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 6, 3, 1, 7, 4, 2, 5, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 14, 15, 12, 13, 11, 8, 10, 9 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 16, 22, 17, 18, 20, 21, 23, 19 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 31, 28, 26, 25, 29, 24, 27, 30 }, + }, + .phys[LP4_PHYS_CH1B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 3, 5, 7, 4, 1, 0, 6, 2 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 14, 13, 10, 11, 15, 9, 8, 12 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 23, 18, 19, 22, 16, 17, 21, 20 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 24, 31, 30, 29, 26, 27, 25, 28 }, + }, +}; + +const struct lpddr4_swizzle_cfg *variant_lpddr4_swizzle_config(void) +{ + return &mc_apl7_lpddr4_swizzle; +}