sb/intel/fsp_rangeley: Fix typo in GPIO Level

Change-Id: I83886820b8c1acceb2007b694361fe8c30c34f7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: David Guckian
2019-01-05 09:58:39 +01:00 · 2019-01-05 09:58:39 +01:00 · e7dd3ca405
parent 5493b4543d
commit e7dd3ca405
1 changed files with 1 additions and 1 deletions
--- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
+++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
@ -93,7 +93,7 @@ Scope(\)
 		GIO2, 8,
 		GIO3, 8,
 		Offset(0x0c),	// GPIO Level
-		GL00, 1,
+		GP00, 1,
 		GP01, 1,
 		GP02, 1,
 		GP0e, 1,