cpu/x86/: Centralize MSEG location calculation
This patch centralizes the MSEG location calculation. In the current implementation, the calculation happens in smm_module_loader and mp_init. When smm_module_loaderv2 was added, this calculation became broken as the original calculation made assumptions based on perm_smbase. The calculation is now located in smm_subregion (tseg_region.c), as the MSEG is located within the TSEG (or SMM); These patches have been tested on a Purism librem-l1um server. Change-Id: Ic17e1a505401c3b2a218826dffae6fe12a5c15c6 Signed-off-by: Eugene Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55628 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -756,9 +756,9 @@ static void asmlinkage smm_do_relocation(void *arg)
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if (CONFIG(STM)) {
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if (is_smm_enabled()) {
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uintptr_t mseg;
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size_t mseg_size;
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mseg = mp_state.perm_smbase +
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(mp_state.perm_smsize - CONFIG_MSEG_SIZE);
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smm_subregion(SMM_SUBREGION_MSEG, &mseg, &mseg_size);
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stm_setup(mseg, p->cpu, runtime->num_cpus,
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perm_smbase,
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@ -368,7 +368,7 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params)
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base += size;
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if (CONFIG(STM))
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base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE;
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base -= CONFIG_BIOS_RESOURCE_LIST_SIZE;
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params->stack_top = base;
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@ -586,8 +586,8 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params)
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/* MSEG starts at the top of SMRAM and works down */
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if (CONFIG(STM)) {
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base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE;
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total_size += CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE;
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base -= CONFIG_BIOS_RESOURCE_LIST_SIZE;
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total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE;
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}
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/* FXSAVE goes below MSEG */
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@ -17,6 +17,7 @@
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#include <cpu/x86/smm.h>
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#include <stage_cache.h>
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#include <types.h>
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#include <inttypes.h>
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/*
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* Subregions within SMM
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@ -25,6 +26,8 @@
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* +-------------------------+
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* | External Stage Cache | SMM_RESERVED_SIZE
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* +-------------------------+
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* | STM | MSEG_SIZE
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* +-------------------------+
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* | code and data |
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* | (TSEG) |
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* +-------------------------+ TSEG
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@ -35,17 +38,24 @@ int smm_subregion(int sub, uintptr_t *start, size_t *size)
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size_t sub_size;
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const size_t ied_size = CONFIG_IED_REGION_SIZE;
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const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
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const size_t mseg_size = CONFIG_MSEG_SIZE;
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smm_region(&sub_base, &sub_size);
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ASSERT(IS_ALIGNED(sub_base, sub_size));
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ASSERT(sub_size > (cache_size + ied_size));
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ASSERT(sub_size > (cache_size + ied_size + mseg_size));
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switch (sub) {
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case SMM_SUBREGION_HANDLER:
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/* Handler starts at the base of TSEG. */
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sub_size -= ied_size;
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sub_size -= cache_size;
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sub_size -= mseg_size;
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break;
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case SMM_SUBREGION_MSEG:
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/* MSEG follows the SMM HANDLER subregion */
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sub_base += sub_size - (ied_size + cache_size + mseg_size);
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sub_size = mseg_size;
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break;
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case SMM_SUBREGION_CACHE:
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/* External cache is in the middle of TSEG. */
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@ -88,11 +98,11 @@ void smm_list_regions(void)
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return;
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printk(BIOS_DEBUG, "SMM Memory Map\n");
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printk(BIOS_DEBUG, "SMRAM : 0x%zx 0x%zx\n", base, size);
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printk(BIOS_DEBUG, "SMRAM : 0x%" PRIxPTR " 0x%zx\n", base, size);
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for (i = 0; i < SMM_SUBREGION_NUM; i++) {
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if (smm_subregion(i, &base, &size))
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continue;
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printk(BIOS_DEBUG, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
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printk(BIOS_DEBUG, " Subregion %d: 0x%" PRIxPTR " 0x%zx\n", i, base, size);
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}
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}
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@ -168,6 +168,8 @@ void smm_region(uintptr_t *start, size_t *size);
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enum {
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/* SMM handler area. */
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SMM_SUBREGION_HANDLER,
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/* MSEG (STM). */
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SMM_SUBREGION_MSEG,
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/* SMM cache region. */
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SMM_SUBREGION_CACHE,
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/* Chipset specific area. */
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