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CBMEM AMD: Remove references to global high_tables_base 

Prepare for removal of globals high_tables_base and _size
by replacing the references with a helper function.

Added set_top_of_ram_once() may be called several times,
but only the first call (with non-zero argument) takes effect.

Change-Id: I5b5f71630f03b6a01e9c8ff96cb78e9da03e5cc3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3894
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki 2013-06-27 08:20:09 +03:00
parent 9c7d73ca3f
commit e7e847cd5c
11 changed files with 69 additions and 121 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/arch/x86/boot/Makefile.inc
View File

@ -2,6 +2,7 @@ ramstage-y += boot.c
ramstage-$(CONFIG_MULTIBOOT) += multiboot.c
ramstage-y += gdt.c
ramstage-y += tables.c
ramstage-y += cbmem.c
ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c

35
src/arch/x86/boot/cbmem.c Normal file
View File

@ -0,0 +1,35 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
*/
#include <console/console.h>
#include <cbmem.h>
#if !CONFIG_DYNAMIC_CBMEM
/* This is for compatibility with old boards only. Any new chipset and board
* must implement get_top_of_ram() for both romstage and ramstage to support
* features like CAR_MIGRATION and CBMEM_CONSOLE.
*/
void set_top_of_ram_once(uint64_t ramtop)
{
if (high_tables_base == 0) {
high_tables_base = ramtop - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
}
printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n",
high_tables_base, high_tables_size);
}
#endif

1
src/include/cbmem.h
View File

@ -136,6 +136,7 @@ void cbmem_add_lb_mem(struct lb_memory *mem);
#ifndef __PRE_RAM__
extern uint64_t high_tables_base, high_tables_size;
void set_top_of_ram_once(uint64_t ramtop);
void set_cbmem_toc(struct cbmem_entry *);
#endif

18
src/northbridge/amd/agesa/family10/northbridge.c
View File

@ -1036,17 +1036,11 @@ static void amdfam10_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(mmio_basek * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
(u32)(high_tables_size / 1024), high_tables_base);
}
}
basek = mmio_basek;
}
@ -1063,15 +1057,11 @@ static void amdfam10_domain_set_resources(device_t dev)
idx += 0x10;
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(limitk * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
}
#if CONFIG_GFXUMA

23
src/northbridge/amd/agesa/family12/northbridge.c
View File

@ -722,20 +722,12 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
ram_resource(dev, idx, basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(mmio_basek * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
(u32)(high_tables_size / 1024),
high_tables_base);
}
}
basek = mmio_basek;
}
if ((basek + sizek) <= 4*1024*1024) {
@ -751,20 +743,13 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
idx += 0x10;
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
0, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base);
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(limitk * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
}
printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",
high_tables_size);
#if CONFIG_GFXUMA
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);

22
src/northbridge/amd/agesa/family14/northbridge.c
View File

@ -716,19 +716,12 @@ static void domain_set_resources(device_t dev)
pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
if (high_tables_base == 0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(mmio_basek * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
(u32)(high_tables_size / 1024), high_tables_base);
}
}
basek = mmio_basek;
}
if ((basek + sizek) <= 4 * 1024 * 1024) {
@ -744,20 +737,13 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG,
"%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0,
mmio_basek, basek, limitk);
if (high_tables_base == 0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base);
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(limitk * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
}
printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",
high_tables_size);
#if CONFIG_GFXUMA
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);

18
src/northbridge/amd/agesa/family15/northbridge.c
View File

@ -807,17 +807,11 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(mmio_basek * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
(u32)(high_tables_size / 1024), high_tables_base);
}
}
basek = mmio_basek;
}
@ -834,15 +828,11 @@ static void domain_set_resources(device_t dev)
idx += 0x10;
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(limitk * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
}
#if CONFIG_GFXUMA

18
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -793,17 +793,11 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(mmio_basek * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
(u32)(high_tables_size / 1024), high_tables_base);
}
}
basek = mmio_basek;
}
@ -821,15 +815,11 @@ static void domain_set_resources(device_t dev)
idx += 0x10;
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(limitk * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
}
#if CONFIG_GFXUMA

18
src/northbridge/amd/agesa/family16kb/northbridge.c
View File

@ -799,17 +799,11 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(mmio_basek * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
(u32)(high_tables_size / 1024), high_tables_base);
}
}
basek = mmio_basek;
}
@ -827,15 +821,11 @@ static void domain_set_resources(device_t dev)
idx += 0x10;
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(limitk * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
}
#if CONFIG_GFXUMA

18
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -1038,17 +1038,11 @@ static void amdfam10_domain_set_resources(device_t dev)
idx += 0x10;
sizek -= pre_sizek;
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(mmio_basek * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
HIGH_MEMORY_SIZE / 1024, high_tables_base);
}
}
#if !CONFIG_AMDMCT
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
@ -1076,15 +1070,11 @@ static void amdfam10_domain_set_resources(device_t dev)
idx += 0x10;
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(limitk * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
}
#if CONFIG_GFXUMA

18
src/northbridge/amd/amdk8/northbridge.c
View File

@ -1042,17 +1042,11 @@ static void amdk8_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(mmio_basek * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
HIGH_MEMORY_SIZE / 1024, high_tables_base);
}
}
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
if(reset_memhole)
@ -1077,15 +1071,11 @@ static void amdk8_domain_set_resources(device_t dev)
idx += 0x10;
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
set_top_of_ram_once(uma_memory_base);
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
set_top_of_ram_once(limitk * 1024);
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
}
#if CONFIG_GFXUMA