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Lenovo X230: new port 

probably a problem in MRC:
- EHCI output failure after sysagent
- no S3
- no MRC cache
- MRC needs watchdog
- less MTRR could be used by some memory map optimisations

Not tested:
- dock (probably doesn't work)
- msata (probably works)
- wwan (probably works)
- mini displayport (probably works)

Blobs:
MRC
VGA Oprom

Change-Id: I5bdb9372971f48e048848d57b6c924b79782dbde
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4679
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Vladimir Serbinenko 2014-01-12 15:26:15 +01:00
parent 2a1d5b061d
commit e7e9502d46
26 changed files with 2512 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/lenovo/Kconfig
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@ -17,6 +17,11 @@ config BOARD_LENOVO_X201
help
Lenovo X201 laptop. Consult wiki for details.
config BOARD_LENOVO_X230
bool "ThinkPad X230"
help
Lenovo X230 laptop. Consult wiki for details.
config BOARD_LENOVO_T60
bool "ThinkPad T60 / T60p"
help
@ -29,6 +34,7 @@ endchoice
source "src/mainboard/lenovo/x60/Kconfig"
source "src/mainboard/lenovo/x201/Kconfig"
source "src/mainboard/lenovo/x230/Kconfig"
source "src/mainboard/lenovo/t60/Kconfig"
config MAINBOARD_VENDOR

83
src/mainboard/lenovo/x230/Kconfig Normal file
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@ -0,0 +1,83 @@
if BOARD_LENOVO_X230
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select EC_LENOVO_PMH7
select EC_LENOVO_H8
select BOARD_ROMSIZE_KB_12288
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select GFXUMA
select EARLY_CBMEM_INIT
# Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE
config HAVE_MRC_CACHE
bool
default n
config HAVE_IFD_BIN
bool
default n
config HAVE_ME_BIN
bool
default n
config MAINBOARD_DIR
string
default lenovo/x230
config MAINBOARD_PART_NUMBER
string
default "2325TLU"
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
config CACHE_ROM_SIZE_OVERRIDE
hex
default 0x800000
config IRQ_SLOT_COUNT
int
default 18
config MAX_CPUS
int
default 8
config USBDEBUG_HCD_INDEX
int
default 2
config DRAM_GATE_GPIO
int
default 10
config VGA_BIOS_FILE
string
default "pci8086,0106.rom"
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0x17aa
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x21fa
config MAINBOARD_VENDOR
string
default "LENOVO"
endif # BOARD_LENOVO_X230

20
src/mainboard/lenovo/x230/Makefile.inc Normal file
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@ -0,0 +1,20 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

26
src/mainboard/lenovo/x230/acpi/ec.asl Normal file
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@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <ec/lenovo/h8/acpi/ec.asl>
Scope(\_SB.PCI0.LPCB.EC)
{
}

13
src/mainboard/lenovo/x230/acpi/gpe.asl Normal file
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@ -0,0 +1,13 @@
Method (_L01, 0, NotSerialized)
{
If (\_SB.PCI0.RP03.HPCS)
{
Sleep (100)
Store (0x01, \_SB.PCI0.RP03.HPCS)
If (\_SB.PCI0.RP03.PDC)
{
Store (0x01, \_SB.PCI0.RP03.PDC)
Notify (\_SB.PCI0.RP03, 0x00)
}
}
}

0
src/mainboard/lenovo/x230/acpi/mainboard.asl Normal file
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74
src/mainboard/lenovo/x230/acpi/platform.asl Normal file
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@ -0,0 +1,74 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* The APM port can be used for generating software SMIs */
OperationRegion (APMP, SystemIO, 0xb2, 2)
Field (APMP, ByteAcc, NoLock, Preserve)
{
APMC, 8, // APM command
APMS, 8 // APM status
}
/* Port 80 POST */
OperationRegion (POST, SystemIO, 0x80, 1)
Field (POST, ByteAcc, Lock, Preserve)
{
DBG0, 8
}
/* SMI I/O Trap */
Method(TRAP, 1, Serialized)
{
Store (Arg0, SMIF) // SMI Function
Store (0, TRP0) // Generate trap
Return (SMIF) // Return value of SMI handler
}
/* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
*
* _PIC is called with a parameter of 0 for i8259 configuration and
* with a parameter of 1 for Local Apic/IOAPIC configuration.
*/
Method(_PIC, 1)
{
// Remember the OS' IRQ routing choice.
Store(Arg0, PICM)
}
/* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
Method(_PTS,1)
{
}
/* The _WAK method is called on system wakeup */
Method(_WAK,1)
{
/* Not implemented. */
Return(Package(){0,0})
}

65
src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl Normal file
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@ -0,0 +1,65 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This is board specific information: IRQ routing for Sandybridge */
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI)
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB
Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF
Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI)
Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH
Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA
})
} Else {
Return (Package() {
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #1 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI #2 0:1a.0
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
})
}
}

1
src/mainboard/lenovo/x230/acpi/superio.asl Normal file
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@ -0,0 +1 @@
#include "../../../../drivers/pc80/ps2_controller.asl"

115
src/mainboard/lenovo/x230/acpi/video.asl Normal file
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@ -0,0 +1,115 @@
/*
* This file is part of the coreboot project.
*
* Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
* Copyright (c) 2013 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include "smi.h"
Scope (\_SB.PCI0.GFX0)
{
Device (LCD0)
{
Name (_ADR, 0x0400)
Name (BRCT, 0)
Name (BRIG, Package (0x12)
{
0x61,
0x61,
0x2,
0x4,
0x5,
0x7,
0x9,
0xb,
0xd,
0x11,
0x14,
0x17,
0x1c,
0x20,
0x27,
0x31,
0x41,
0x61,
})
Method (_BCL, 0, NotSerialized)
{
Store (1, BRCT)
Return (BRIG)
}
Method (_BCM, 1, NotSerialized)
{
Store (ShiftLeft (Arg0, 4), ^^BCLV)
Store (0x80000000, ^^CR1)
Store (0x061a061a, ^^CR2)
}
Method (_BQC, 0, NotSerialized)
{
Store (^^BCLV, Local0)
ShiftRight (Local0, 4, Local0)
Return (Local0)
}
Method(BRID, 1, NotSerialized)
{
Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
If (LEqual (Local0, Ones))
{
Return (0x11)
}
Return (Local0)
}
/* Using Notify is the right way. But Windows doesn't handle
it well. So use both method in a way to avoid double action.
*/
Method (DECB, 0, NotSerialized)
{
If (BRCT)
{
Notify (LCD0, 0x87)
} Else {
Store (BRID (_BQC ()), Local0)
If (LNotEqual (Local0, 2))
{
Decrement (Local0)
}
_BCM (DerefOf (Index (BRIG, Local0)))
}
}
Method (INCB, 0, NotSerialized)
{
If (BRCT)
{
Notify (LCD0, 0x86)
} Else {
Store (BRID (_BQC ()), Local0)
If (LNotEqual (Local0, 0x11))
{
Increment (Local0)
}
_BCM (DerefOf (Index (BRIG, Local0)))
}
}
}
}

256
src/mainboard/lenovo/x230/acpi_tables.c Normal file
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@ -0,0 +1,256 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <cbmem.h>
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode[];
#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
static void acpi_update_thermal_table(global_nvs_t *gnvs)
{
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
}
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
memset((void *)gnvs, 0, sizeof(*gnvs));
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;
gnvs->s3u1 = 0;
/* Disable USB ports in S5 by default */
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
/* CBMEM TOC */
gnvs->cmem = (u32)get_cbmem_toc();
/* IGD Displays */
gnvs->ndid = 3;
gnvs->did[0] = 0x80000100;
gnvs->did[1] = 0x80000240;
gnvs->did[2] = 0x80000410;
gnvs->did[3] = 0x80000410;
gnvs->did[4] = 0x00000005;
// the lid is open by default.
gnvs->lids = 1;
acpi_update_thermal_table(gnvs);
}
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
current = acpi_create_madt_lapics(current);
/* IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
2, IO_APIC_ADDR, 0);
/* INT_SRC_OVR */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
return current;
}
unsigned long acpi_fill_ssdt_generator(unsigned long current,
const char *oem_table_id)
{
generate_cpu_entries();
return (unsigned long) (acpigen_get_current());
}
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
return current;
}
unsigned long acpi_fill_srat(unsigned long current)
{
/* No NUMA, no SRAT */
return current;
}
#define ALIGN_CURRENT current = (ALIGN(current, 16))
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
int i;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_xsdt_t *xsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_mcfg_t *mcfg;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
#if CONFIG_HAVE_ACPI_SLIC
acpi_header_t *slic;
#endif
acpi_header_t *ssdt;
acpi_header_t *dsdt;
current = start;
/* Align ACPI tables to 16byte */
ALIGN_CURRENT;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
ALIGN_CURRENT;
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
ALIGN_CURRENT;
xsdt = (acpi_xsdt_t *) current;
current += sizeof(acpi_xsdt_t);
ALIGN_CURRENT;
/* clear all table memory */
memset((void *) start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, xsdt);
acpi_write_rsdt(rsdt);
acpi_write_xsdt(xsdt);
printk(BIOS_DEBUG, "ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
ALIGN_CURRENT;
acpi_create_facs(facs);
printk(BIOS_DEBUG, "ACPI: * DSDT\n");
dsdt = (acpi_header_t *) current;
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length);
ALIGN_CURRENT;
printk(BIOS_DEBUG, "ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
ALIGN_CURRENT;
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);
/*
* We explicitly add these tables later on:
*/
printk(BIOS_DEBUG, "ACPI: * HPET\n");
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
ALIGN_CURRENT;
acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet);
/* If we want to use HPET Timers Linux wants an MADT */
printk(BIOS_DEBUG, "ACPI: * MADT\n");
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
ALIGN_CURRENT;
acpi_add_table(rsdp, madt);
printk(BIOS_DEBUG, "ACPI: * MCFG\n");
mcfg = (acpi_mcfg_t *) current;
acpi_create_mcfg(mcfg);
current += mcfg->header.length;
ALIGN_CURRENT;
acpi_add_table(rsdp, mcfg);
/* Pack GNVS into the ACPI table area */
for (i=0; i < dsdt->length; i++) {
if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
"DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
acpi_save_gnvs(current);
break;
}
}
/* And fill it */
acpi_create_gnvs((global_nvs_t *)current);
/* And tell SMI about it */
smm_setup_structures((void *)current, NULL, NULL);
current += sizeof(global_nvs_t);
ALIGN_CURRENT;
/* We patched up the DSDT, so we need to recalculate the checksum */
dsdt->checksum = 0;
dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
dsdt->length);
#if CONFIG_HAVE_ACPI_SLIC
printk(BIOS_DEBUG, "ACPI: * SLIC\n");
slic = (acpi_header_t *)current;
current += acpi_create_slic(current);
ALIGN_CURRENT;
acpi_add_table(rsdp, slic);
#endif
printk(BIOS_DEBUG, "ACPI: * SSDT\n");
ssdt = (acpi_header_t *)current;
acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
current += ssdt->length;
acpi_add_table(rsdp, ssdt);
ALIGN_CURRENT;
printk(BIOS_DEBUG, "current = %lx\n", current);
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}

6
src/mainboard/lenovo/x230/board_info.txt Normal file
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@ -0,0 +1,6 @@
Category: laptop
Board name: X230
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: n

18
src/mainboard/lenovo/x230/cmos.default Normal file
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@ -0,0 +1,18 @@
boot_option=Fallback
last_boot=Fallback
baud_rate=115200
debug_level=Spew
power_on_after_fail=Enable
nmi=Enable
volume=0x3
first_battery=Primary
bluetooth=Enable
wwan=Enable
wlan=Enable
touchpad=Enable
sata_mode=AHCI
fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
hyper_threading=Enable
backlight=Both

157
src/mainboard/lenovo/x230/cmos.layout Normal file
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@ -0,0 +1,157 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
# -----------------------------------------------------------------
entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
# -----------------------------------------------------------------
# Status Register A
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
# -----------------------------------------------------------------
# Status Register B
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
385 1 e 4 last_boot
388 4 r 0 reboot_bits
#390 2 r 0 unused?
# -----------------------------------------------------------------
# coreboot config options: console
392 3 e 5 baud_rate
395 4 e 6 debug_level
#399 1 r 0 unused
400 8 h 0 volume
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: EC
411 1 e 8 first_battery
412 1 e 1 bluetooth
413 1 e 1 wwan
414 1 e 1 touchpad
415 1 e 1 wlan
416 1 e 1 trackpoint
417 1 e 1 fn_ctrl_swap
418 1 e 1 sticky_fn
#419 2 r 0 unused
421 1 e 9 sata_mode
422 2 e 10 backlight
# coreboot config options: cpu
424 1 e 2 hyper_threading
#425 559 r 0 unused
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
960 16 r 0 mrc_scrambler_seed_chk
# coreboot config options: check sums
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Disable
7 1 Enable
7 2 Keep
8 0 Secondary
8 1 Primary
9 0 AHCI
9 1 Compatible
10 0 Both
10 1 Keyboard only
10 2 Thinklight only
10 3 None
# -----------------------------------------------------------------
checksums
checksum 392 415 984

135
src/mainboard/lenovo/x230/devicetree.cb Normal file
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chip northbridge/intel/sandybridge
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Enable Panel as LVDS and configure power delays
register "gpu_panel_port_select" = "0" # LVDS
register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end
end
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
# Coordinate with HW_ALL
register "pstate_coord_type" = "0xfe"
register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 off end # PCIe Bridge for discrete graphics
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "pirqa_routing" = "0x8b"
register "pirqb_routing" = "0x8a"
register "pirqc_routing" = "0x8b"
register "pirqd_routing" = "0x8b"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2"
register "gpi8_routing" = "2"
# Enable SATA ports 0 & 1
register "sata_port_map" = "0x3"
# Set max SATA speed to 6.0 Gb/s
register "sata_interface_speed_support" = "0x3"
register "gen1_dec" = "0x7c1601"
register "gen2_dec" = "0x0c15e1"
register "gen4_dec" = "0x0c06a1"
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
device pci 14.0 on end # USB 3.0 Controller
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 on end # Intel Gigabit Ethernet
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2
device pci 1c.2 on end # PCIe Port #3 (expresscard)
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on #LPC bridge
chip ec/lenovo/pmh7
device pnp ff.1 on # dummy
end
register "backlight_enable" = "0x01"
register "dock_event_enable" = "0x01"
end
chip ec/lenovo/h8
device pnp ff.2 on # dummy
io 0x60 = 0x62
io 0x62 = 0x66
io 0x64 = 0x1600
io 0x66 = 0x1604
end
register "config0" = "0xa6"
register "config1" = "0x09"
register "config2" = "0xa0"
register "config3" = "0xe0"
register "has_keyboard_backlight" = "1"
register "beepmask0" = "0x00"
register "beepmask1" = "0x86"
register "has_power_management_beeps" = "0"
register "event2_enable" = "0xff"
register "event3_enable" = "0xff"
register "event4_enable" = "0xd0"
register "event5_enable" = "0xfc"
register "event6_enable" = "0x00"
register "event7_enable" = "0x01"
register "event8_enable" = "0x7b"
register "event9_enable" = "0xff"
register "eventa_enable" = "0x01"
register "eventb_enable" = "0x00"
register "eventc_enable" = "0xff"
register "eventd_enable" = "0xff"
register "evente_enable" = "0x0d"
end
end # LPC bridge
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 on end # Thermal
end
end
end

60
src/mainboard/lenovo/x230/dsdt.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define THINKPAD_EC_GPE 17
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define RP03_IS_EXPRESSCARD 1
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20110725 // OEM revision
)
{
// Some generic macros
#include "acpi/platform.asl"
#include "acpi/mainboard.asl"
// global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
}
}
#include "acpi/video.asl"
/* Chipset specific sleep states */
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
}

159
src/mainboard/lenovo/x230/fadt.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <string.h>
#include <device/pci.h>
#include <arch/acpi.h>
#include <cpu/x86/smm.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
0x40) & 0xfffe;
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
header->revision = 3;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, "CORE", 4);
header->asl_compiler_revision = 1;
fadt->firmware_ctrl = (unsigned long) facs;
fadt->dsdt = (unsigned long) dsdt;
fadt->model = 1;
fadt->preferred_pm_profile = PM_MOBILE;
fadt->sci_int = 0x9;
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0;
fadt->pm1a_evt_blk = pmbase;
fadt->pm1b_evt_blk = 0x0;
fadt->pm1a_cnt_blk = pmbase + 0x4;
fadt->pm1b_cnt_blk = 0x0;
fadt->pm2_cnt_blk = pmbase + 0x50;
fadt->pm_tmr_blk = pmbase + 0x8;
fadt->gpe0_blk = pmbase + 0x20;
fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
fadt->p_lvl2_lat = 101; /* c2 not supported */
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
fadt->duty_offset = 1;
fadt->duty_width = 3;
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->century = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
fadt->flags = ACPI_FADT_WBINVD |
ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_RESET_REGISTER |
ACPI_FADT_SEALED_CASE |
ACPI_FADT_S4_RTC_WAKE |
ACPI_FADT_PLATFORM_CLOCK;
fadt->reset_reg.space_id = 1;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0;
fadt->reset_value = 6;
fadt->x_firmware_ctl_l = (unsigned long)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (unsigned long)dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.addrl = pmbase;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = 0;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = 0;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 8;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 128;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = pmbase + 0x20;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = 0x0;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum =
acpi_checksum((void *) fadt, header->length);
}

305
src/mainboard/lenovo/x230/gpio.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef X230_GPIO_H
#define X230_GPIO_H
#include "southbridge/intel/bd82x6x/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_GPIO,
.gpio2 = GPIO_MODE_GPIO,
.gpio3 = GPIO_MODE_GPIO,
.gpio4 = GPIO_MODE_GPIO,
.gpio5 = GPIO_MODE_GPIO,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_NATIVE,
.gpio10 = GPIO_MODE_GPIO,
.gpio11 = GPIO_MODE_NATIVE,
.gpio12 = GPIO_MODE_NATIVE,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_NATIVE,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_NATIVE,
.gpio17 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_NATIVE,
.gpio19 = GPIO_MODE_NATIVE,
.gpio20 = GPIO_MODE_NATIVE,
.gpio21 = GPIO_MODE_GPIO,
.gpio22 = GPIO_MODE_GPIO,
.gpio23 = GPIO_MODE_NATIVE,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_NATIVE,
.gpio26 = GPIO_MODE_NATIVE,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio29 = GPIO_MODE_GPIO,
.gpio30 = GPIO_MODE_NATIVE,
.gpio31 = GPIO_MODE_NATIVE,
};
const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio2 = GPIO_DIR_INPUT,
.gpio3 = GPIO_DIR_INPUT,
.gpio4 = GPIO_DIR_INPUT,
.gpio5 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_OUTPUT,
.gpio9 = GPIO_DIR_INPUT,
.gpio10 = GPIO_DIR_OUTPUT,
.gpio11 = GPIO_DIR_INPUT,
.gpio12 = GPIO_DIR_OUTPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_OUTPUT,
.gpio16 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_INPUT,
.gpio18 = GPIO_DIR_INPUT,
.gpio19 = GPIO_DIR_INPUT,
.gpio20 = GPIO_DIR_INPUT,
.gpio21 = GPIO_DIR_INPUT,
.gpio22 = GPIO_DIR_OUTPUT,
.gpio23 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio25 = GPIO_DIR_INPUT,
.gpio26 = GPIO_DIR_INPUT,
.gpio27 = GPIO_DIR_INPUT,
.gpio28 = GPIO_DIR_OUTPUT,
.gpio29 = GPIO_DIR_OUTPUT,
.gpio30 = GPIO_DIR_OUTPUT,
.gpio31 = GPIO_DIR_INPUT
};
const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio0 = GPIO_LEVEL_HIGH,
.gpio1 = GPIO_LEVEL_HIGH,
.gpio2 = GPIO_LEVEL_LOW,
.gpio3 = GPIO_LEVEL_HIGH,
.gpio4 = GPIO_LEVEL_HIGH,
.gpio5 = GPIO_LEVEL_HIGH,
.gpio6 = GPIO_LEVEL_HIGH,
.gpio7 = GPIO_LEVEL_HIGH,
.gpio8 = GPIO_LEVEL_LOW,
.gpio9 = GPIO_LEVEL_HIGH,
.gpio10 = GPIO_LEVEL_HIGH,
.gpio11 = GPIO_LEVEL_HIGH,
.gpio12 = GPIO_LEVEL_HIGH,
.gpio13 = GPIO_LEVEL_HIGH,
.gpio14 = GPIO_LEVEL_HIGH,
.gpio15 = GPIO_LEVEL_LOW,
.gpio16 = GPIO_LEVEL_HIGH,
.gpio17 = GPIO_LEVEL_HIGH,
.gpio18 = GPIO_LEVEL_HIGH,
.gpio19 = GPIO_LEVEL_HIGH,
.gpio20 = GPIO_LEVEL_HIGH,
.gpio21 = GPIO_LEVEL_HIGH,
.gpio22 = GPIO_LEVEL_HIGH,
.gpio23 = GPIO_LEVEL_HIGH,
.gpio24 = GPIO_LEVEL_LOW,
.gpio25 = GPIO_LEVEL_HIGH,
.gpio26 = GPIO_LEVEL_HIGH,
.gpio27 = GPIO_LEVEL_LOW,
.gpio28 = GPIO_LEVEL_LOW,
.gpio29 = GPIO_LEVEL_HIGH,
.gpio30 = GPIO_LEVEL_HIGH,
.gpio31 = GPIO_LEVEL_LOW,
};
const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio1 = GPIO_INVERT,
.gpio6 = GPIO_INVERT,
.gpio13 = GPIO_INVERT,
};
const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_NATIVE,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio36 = GPIO_MODE_GPIO,
.gpio37 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
.gpio40 = GPIO_MODE_NATIVE,
.gpio41 = GPIO_MODE_NATIVE,
.gpio42 = GPIO_MODE_NATIVE,
.gpio43 = GPIO_MODE_GPIO,
.gpio44 = GPIO_MODE_NATIVE,
.gpio45 = GPIO_MODE_NATIVE,
.gpio46 = GPIO_MODE_NATIVE,
.gpio47 = GPIO_MODE_NATIVE,
.gpio48 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_GPIO,
.gpio50 = GPIO_MODE_GPIO,
.gpio51 = GPIO_MODE_GPIO,
.gpio52 = GPIO_MODE_GPIO,
.gpio53 = GPIO_MODE_GPIO,
.gpio54 = GPIO_MODE_GPIO,
.gpio55 = GPIO_MODE_GPIO,
.gpio56 = GPIO_MODE_NATIVE,
.gpio57 = GPIO_MODE_GPIO,
.gpio58 = GPIO_MODE_NATIVE,
.gpio59 = GPIO_MODE_NATIVE,
.gpio60 = GPIO_MODE_NATIVE,
.gpio61 = GPIO_MODE_NATIVE,
.gpio62 = GPIO_MODE_NATIVE,
.gpio63 = GPIO_MODE_NATIVE,
};
const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_INPUT,
.gpio33 = GPIO_DIR_INPUT,
.gpio34 = GPIO_DIR_OUTPUT,
.gpio35 = GPIO_DIR_INPUT,
.gpio36 = GPIO_DIR_INPUT,
.gpio37 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
.gpio40 = GPIO_DIR_INPUT,
.gpio41 = GPIO_DIR_INPUT,
.gpio42 = GPIO_DIR_INPUT,
.gpio43 = GPIO_DIR_OUTPUT,
.gpio44 = GPIO_DIR_INPUT,
.gpio45 = GPIO_DIR_INPUT,
.gpio46 = GPIO_DIR_INPUT,
.gpio47 = GPIO_DIR_INPUT,
.gpio48 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_INPUT,
.gpio50 = GPIO_DIR_INPUT,
.gpio51 = GPIO_DIR_OUTPUT,
.gpio52 = GPIO_DIR_OUTPUT,
.gpio53 = GPIO_DIR_OUTPUT,
.gpio54 = GPIO_DIR_INPUT,
.gpio55 = GPIO_DIR_OUTPUT,
.gpio56 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_INPUT,
.gpio58 = GPIO_DIR_INPUT,
.gpio59 = GPIO_DIR_INPUT,
.gpio60 = GPIO_DIR_INPUT,
.gpio61 = GPIO_DIR_OUTPUT,
.gpio62 = GPIO_DIR_OUTPUT,
.gpio63 = GPIO_DIR_OUTPUT,
};
const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_HIGH,
.gpio33 = GPIO_LEVEL_HIGH,
.gpio34 = GPIO_LEVEL_LOW,
.gpio35 = GPIO_LEVEL_LOW,
.gpio36 = GPIO_LEVEL_LOW,
.gpio37 = GPIO_LEVEL_LOW,
.gpio38 = GPIO_LEVEL_HIGH,
.gpio39 = GPIO_LEVEL_LOW,
.gpio40 = GPIO_LEVEL_HIGH,
.gpio41 = GPIO_LEVEL_HIGH,
.gpio42 = GPIO_LEVEL_HIGH,
.gpio43 = GPIO_LEVEL_HIGH,
.gpio44 = GPIO_LEVEL_HIGH,
.gpio45 = GPIO_LEVEL_HIGH,
.gpio46 = GPIO_LEVEL_HIGH,
.gpio47 = GPIO_LEVEL_HIGH,
.gpio48 = GPIO_LEVEL_HIGH,
.gpio49 = GPIO_LEVEL_HIGH,
.gpio50 = GPIO_LEVEL_HIGH,
.gpio51 = GPIO_LEVEL_HIGH,
.gpio52 = GPIO_LEVEL_HIGH,
.gpio53 = GPIO_LEVEL_HIGH,
.gpio54 = GPIO_LEVEL_HIGH,
.gpio55 = GPIO_LEVEL_HIGH,
.gpio56 = GPIO_LEVEL_HIGH,
.gpio57 = GPIO_LEVEL_HIGH,
.gpio58 = GPIO_LEVEL_HIGH,
.gpio59 = GPIO_LEVEL_HIGH,
.gpio60 = GPIO_LEVEL_HIGH,
.gpio61 = GPIO_LEVEL_HIGH,
.gpio62 = GPIO_LEVEL_LOW,
.gpio63 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio64 = GPIO_MODE_GPIO,
.gpio65 = GPIO_MODE_GPIO,
.gpio66 = GPIO_MODE_GPIO,
.gpio67 = GPIO_MODE_GPIO,
.gpio68 = GPIO_MODE_GPIO,
.gpio69 = GPIO_MODE_GPIO,
.gpio70 = GPIO_MODE_GPIO,
.gpio71 = GPIO_MODE_GPIO,
.gpio72 = GPIO_MODE_NATIVE,
.gpio73 = GPIO_MODE_NATIVE,
.gpio74 = GPIO_MODE_NATIVE,
.gpio75 = GPIO_MODE_NATIVE,
};
const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio64 = GPIO_DIR_INPUT,
.gpio65 = GPIO_DIR_INPUT,
.gpio66 = GPIO_DIR_INPUT,
.gpio67 = GPIO_DIR_INPUT,
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio70 = GPIO_DIR_INPUT,
.gpio71 = GPIO_DIR_INPUT,
.gpio72 = GPIO_DIR_INPUT,
.gpio73 = GPIO_DIR_INPUT,
.gpio74 = GPIO_DIR_INPUT,
.gpio75 = GPIO_DIR_INPUT,
};
const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio64 = GPIO_LEVEL_HIGH,
.gpio65 = GPIO_LEVEL_HIGH,
.gpio66 = GPIO_LEVEL_HIGH,
.gpio67 = GPIO_LEVEL_HIGH,
.gpio68 = GPIO_LEVEL_LOW,
.gpio69 = GPIO_LEVEL_LOW,
.gpio70 = GPIO_LEVEL_HIGH,
.gpio71 = GPIO_LEVEL_HIGH,
.gpio72 = GPIO_LEVEL_HIGH,
.gpio73 = GPIO_LEVEL_HIGH,
.gpio74 = GPIO_LEVEL_HIGH,
.gpio75 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_map x230_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.invert = &pch_gpio_set1_invert,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
},
};
#endif

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Vendor Name : IDT
* Vendor ID : 0x10ec0269
* Subsystem ID : 0x17aa21fa
* Revision ID : 0x100303
*/
static const u32 mainboard_cim_verb_data[] = {
/* coreboot specific header */
0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC
0x17aa21fa, // Subsystem ID
0x0000007d, // Number of 4 dword sets
/* Bits 31:28 - Codec Address */
/* Bits 27:20 - NID */
/* Bits 19:8 - Verb ID */
/* Bits 7:0 - Payload */
/* NID 0x01 - NodeInfo */
0x001720FA,
0x00172121,
0x001722AA,
0x00172317,
/* NID 0x0A - External Microphone Connector
* Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq)
*/
0x00A71C20,
0x00A71D10,
0x00A71EA1,
0x00A71F04,
/* NID 0x0B - Headphone Connector
* Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq)
*/
0x00B71C1F,
0x00B71D10,
0x00B71E21,
0x00B71F04,
/* NID 0x0C - Not connected
* Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq)
*/
0x00C71CF0,
0x00C71D00,
0x00C71EF0,
0x00C71F40,
/* NID 0x0D - Internal Speakers
* Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq)
*/
0x00D71C10,
0x00D71D01,
0x00D71E17,
0x00D71F90,
/* NID 0x0F - Not connected
* Config=0x40F000F0
*/
0x00F71CF0,
0x00F71D00,
0x00F71EF0,
0x00F71F40,
/* NID 0x11 - Internal Microphone
* Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq)
*/
0x01171C40,
0x01171D01,
0x01171EA3,
0x01171FD5,
0x01271C40,
0x01271D01,
0x01271EA6,
0x01271F90,
0x01471C10,
0x01471D01,
0x01471E17,
0x01471F90,
0x01571C20,
0x01571D10,
0x01571E21,
0x01571F03,
0x01871C30,
0x01871D18,
0x01871EA1,
0x01871F03,
0x01971CF0,
0x01971D11,
0x01971E11,
0x01971F41,
0x01970804,
0x01870803,
0x01470740,
0x00970600,
0x00370600,
0x00270600,
0x00270600,
0x00270600,
0x01A71CF0,
0x01A71D11,
0x01A71E11,
0x01A71F41,
0x01D71C05,
0x01D71D82,
0x01D71E13,
0x01D71F40,
0x01E71CF0,
0x01E71D11,
0x01E71E11,
0x01E71F41,
/*
* Hardware EQ Parameters
* Sample Rate 88200
*/
0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80,
0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981,
0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80,
0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80,
0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E,
0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80,
0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1,
0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80,
0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E,
0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80,
0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983,
0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80,
0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D,
0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80,
0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C,
0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80,
0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3,
0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80,
0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F,
0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80,
0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982,
0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80,
0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E,
0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80,
0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D,
0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80,
0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2,
0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80,
0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F,
0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80,
0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E,
0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80,
0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937,
0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80,
0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971,
0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80,
0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9,
0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80,
0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942,
0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80,
0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C,
0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80,
0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934,
0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80,
0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963,
0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80,
0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9,
0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80,
0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80,
/*
* Hardware EQ Parameters
* Sample Rate 96000
*/
0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80,
0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981,
0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80,
0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80,
0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E,
0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80,
0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1,
0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80,
0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E,
0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80,
0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983,
0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80,
0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D,
0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80,
0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C,
0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80,
0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3,
0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80,
0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F,
0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80,
0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982,
0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80,
0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E,
0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80,
0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D,
0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80,
0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1,
0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80,
0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F,
0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80,
0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D,
0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80,
0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938,
0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80,
0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972,
0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80,
0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8,
0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80,
0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941,
0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80,
0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999,
0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80,
0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934,
0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80,
0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966,
0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80,
0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9,
0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80,
0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80,
/* SAFEDSP Parameters */
0x022782C1, 0x02277127, 0x02277227, 0x02278801,
0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14,
0x02278B0F, 0x0017B008,
/* Misc entries */
0x00B707C0, /* Enable PortB as Output with HP amp */
0x00D70740, /* Enable PortD as Output */
0x0017A200, /* Disable ClkEn of PortSenseTst */
0x0017C621, /* Slave Port - Port A used as microphone input for
combo Jack
Master Port - Port B used for Jack Presence Detect
Enable Combo Jack Detection */
0x0017A208, /* Enable ClkEn of PortSenseTst */
0x00170500, /* Set power state to D0 */
/* --- Next Codec --- */
/* Vendor Name : Intel
* Vendor ID : 0x80862806
* Subsystem ID : 0x80860101
* Revision ID : 0x100000
*/
/* coreboot specific header */
0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI
0x80860101, // Subsystem ID
0x00000004, // Number of IDs
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
0x30172001,
0x30172101,
0x30172286,
0x30172380,
/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
0x30571c10,
0x30571d00,
0x30571e56,
0x30571f18,
/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
0x30671c20,
0x30671d00,
0x30671e56,
0x30671f18,
/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
0x30771c30,
0x30771d00,
0x30771e56,
0x30771f18
};
static const u32 mainboard_pc_beep_verbs[] = {
0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
};
static const u32 mainboard_pc_beep_verbs_size =
sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011-2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#if CONFIG_VGA_ROM_RUN
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include "hda_verb.h"
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
#include <device/pci.h>
#include <cbfs.h>
#include <pc80/keyboard.h>
void mainboard_suspend_resume(void)
{
/* Call SMM finalize() handlers before resume */
outb(0xcb, 0xb2);
}
#if CONFIG_VGA_ROM_RUN
static int int15_handler(void)
{
int res = 0;
printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
__func__, X86_AX);
switch (X86_AX) {
case 0x5f34:
/*
* Set Panel Fitting Hook:
* bit 2 = Graphics Stretching
* bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2)
* 0 = video bios default
*/
X86_AX = 0x005f;
X86_CL = 0x00; /* Use video bios default */
res = 1;
break;
case 0x5f35:
/*
* Boot Display Device Hook:
* bit 0 = CRT
* bit 1 = TV (eDP)
* bit 2 = EFP
* bit 3 = LFP
* bit 4 = CRT2
* bit 5 = TV2 (eDP)
* bit 6 = EFP2
* bit 7 = LFP2
*/
X86_AX = 0x005f;
X86_CX = 0x0000; /* Use video bios default */
res = 1;
break;
case 0x5f51:
/*
* Hook to select active LFP configuration:
* 00h = No LVDS, VBIOS does not enable LVDS
* 01h = Int-LVDS, LFP driven by integrated LVDS decoder
* 02h = SVDO-LVDS, LFP driven by SVDO decoder
* 03h = eDP, LFP Driven by Int-DisplayPort encoder
*/
X86_AX = 0x005f;
X86_CX = 0x0001; /* Int-LVDS */
res = 1;
break;
case 0x5f70:
switch (X86_CH) {
case 0:
/* Get Mux */
X86_AX = 0x005f;
X86_CX = 0x0000;
res = 1;
break;
case 1:
/* Set Mux */
X86_AX = 0x005f;
X86_CX = 0x0000;
res = 1;
break;
case 2:
/* Get SG/Non-SG mode */
X86_AX = 0x005f;
X86_CX = 0x0000;
res = 1;
break;
default:
/* Interrupt was not handled */
printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
X86_CH);
break;
}
break;
default:
printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
break;
}
return res;
}
#endif
const char *smbios_mainboard_version(void)
{
return "ThinkPad X230";
}
/* Audio Setup */
extern const u32 *cim_verb_data;
extern u32 cim_verb_data_size;
extern const u32 *pc_beep_verbs;
extern u32 pc_beep_verbs_size;
static void verb_setup(void)
{
cim_verb_data = mainboard_cim_verb_data;
cim_verb_data_size = sizeof(mainboard_cim_verb_data);
pc_beep_verbs = mainboard_pc_beep_verbs;
pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
}
static void mainboard_init(device_t dev)
{
RCBA32(0x38c8) = 0x00002005;
RCBA32(0x38c4) = 0x00802005;
RCBA32(0x38c0) = 0x00000007;
/* This sneaked in here, because X201 SuperIO chip isn't really
connected to anything and hence we don't init it.
*/
pc_keyboard_init(0);
/* Enable expresscard hotplug events. */
pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)),
0xd8,
pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0xd8)
| (1 << 30));
pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 2)),
0x42, 0x142);
}
// mainboard_enable is executed as first thing after
// enumerate_buses().
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
#if CONFIG_VGA_ROM_RUN
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif
verb_setup();
}
void h8_mainboard_init_dock (void);
void h8_mainboard_init_dock (void)
{
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

283
src/mainboard/lenovo/x230/romstage.c Normal file
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@ -0,0 +1,283 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <string.h>
#include <lib.h>
#include <timestamp.h>
#include <arch/byteorder.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <cbmem.h>
#include <console/console.h>
#include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit.h"
#include "southbridge/intel/bd82x6x/pch.h"
#include "southbridge/intel/bd82x6x/gpio.h"
#include <arch/cpu.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include "gpio.h"
#include <cbfs.h>
static void pch_enable_lpc(void)
{
/* X230 EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
COMA_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, 0xac,
0x80010000);
}
static void rcba_config(void)
{
/*
* GFX INTA -> PIRQA (MSI)
* D28IP_P1IP WLAN INTA -> PIRQB
* D28IP_P2IP ETH0 INTB -> PIRQF
* D28IP_P3IP SDCARD INTC -> PIRQD
* D29IP_E1P EHCI1 INTA -> PIRQD
* D26IP_E2P EHCI2 INTA -> PIRQF
* D31IP_SIP SATA INTA -> PIRQB (MSI)
* D31IP_SMIP SMBUS INTB -> PIRQH
* D31IP_TTIP THRT INTC -> PIRQA
* D27IP_ZIP HDA INTA -> PIRQA (MSI)
*
* Trackpad interrupt is edge triggered and cannot be shared.
* TRACKPAD -> PIRQG
*/
/* Device interrupt pin register (board specific) */
RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
RCBA32(D29IP) = (INTA << D29IP_E1P);
RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
(INTC << D28IP_P3IP);
RCBA32(D27IP) = (INTA << D27IP_ZIP);
RCBA32(D26IP) = (INTA << D26IP_E2P);
RCBA32(D25IP) = (NOINT << D25IP_LIP);
RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
/* Device interrupt route registers */
DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
/* Disable unused devices (board specific) */
RCBA32(FD) = 0x17f81fe3;
RCBA32(BUC) = 0;
}
void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
u32 pm1_cnt;
u16 pm1_sts;
if (MCHBAR16(SSKPD) == 0xCAFE) {
outb(0x6, 0xcf9);
hlt ();
}
struct pei_data pei_data = {
pei_version: PEI_VERSION,
mchbar: DEFAULT_MCHBAR,
dmibar: DEFAULT_DMIBAR,
epbar: DEFAULT_EPBAR,
pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
smbusbar: SMBUS_IO_BASE,
wdbbar: 0x4000000,
wdbsize: 0x1000,
hpet_address: CONFIG_HPET_ADDRESS,
rcba: DEFAULT_RCBABASE,
pmbase: DEFAULT_PMBASE,
gpiobase: DEFAULT_GPIOBASE,
thermalbase: 0xfed08000,
system_type: 0, // 0 Mobile, 1 Desktop/Server
tseg_size: CONFIG_SMM_TSEG_SIZE,
spd_addresses: { 0xA0, 0x00,0xA2,0x00 },
ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
ec_present: 1,
gbe_enable: 1,
ddr3lv_support: 0,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
dimm_channel0_disabled: 2,
dimm_channel1_disabled: 2,
max_ddr3_freq: 1600,
usb_port_config: {
/* enabled usb oc pin length */
{ 1, 0, 0x0080 }, /* P0 (left, fan side), OC 0 */
{ 1, 1, 0x0080 }, /* P1 (left touchpad side), OC 1 */
{ 1, 3, 0x0080 }, /* P2: dock, OC 3 */
{ 1, 0, 0x0040 }, /* P3: wwan, no OC */
{ 0, 0, 0x0000 }, /* P4: Empty */
{ 1, 0, 0x0080 }, /* P5: Expresscard, no OC */
{ 0, 0, 0x0000 }, /* P6: Empty */
{ 1, 0, 0x0080 }, /* P7: dock, no OC */
{ 0, 0, 0x0000 }, /* P8: Empty */
{ 1, 5, 0x0080 }, /* P9: Right (EHCI debug), OC 5 */
{ 1, 0, 0x0040 }, /* P10: fingerprint reader, no OC */
{ 1, 0, 0x0040 }, /* P11: bluetooth, no OC. */
{ 1, 0, 0x0040 }, /* P12: wlan, no OC */
{ 1, 0, 0x0080 }, /* P13: webcam, no OC */
},
ddr_refresh_rate_config: 2, /* Force double refresh rate */
};
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
pch_enable_lpc();
/* Enable GPIOs */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&x230_gpio_map);
/* Initialize console device(s) */
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
/* Check PM1_STS[15] to see if we are waking from Sx */
pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
/* Read PM1_CNT[12:10] to determine which Sx state */
pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
#endif
}
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
enable_smbus();
/* Prepare USB controller early in S3 resume */
if (boot_mode == 2)
enable_usb_bar();
post_code(0x39);
post_code(0x3a);
pei_data.boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
/* MRC.bin has a bug and sometimes halts (instead of reboot?).
*/
if (boot_mode != 2)
{
RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */
outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */
}
sdram_initialize(&pei_data);
if (boot_mode != 2)
{
RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
}
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3c);
rcba_config();
post_code(0x3d);
quick_ram_check();
post_code(0x3e);
MCHBAR16(SSKPD) = 0xCAFE;
cbmem_was_initted = !cbmem_initialize();
#if CONFIG_HAVE_ACPI_RESUME
/* If there is no high memory area, we didn't boot before, so
* this is not a resume. In that case we just create the cbmem toc.
*/
*(u32 *)CBMEM_BOOT_MODE = 0;
*(u32 *)CBMEM_RESUME_BACKUP = 0;
if ((boot_mode == 2) && cbmem_was_initted) {
void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
if (resume_backup_memory) {
*(u32 *)CBMEM_BOOT_MODE = boot_mode;
*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
}
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
} else if (boot_mode == 2) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
hlt();
} else {
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
}
#endif
post_code(0x3f);
timestamp_add_now(TS_END_ROMSTAGE);
}

0
src/mainboard/lenovo/x230/smi.h Normal file
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174
src/mainboard/lenovo/x230/smihandler.c Normal file
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@ -0,0 +1,174 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <ec/acpi/ec.h>
#include <pc80/mc146818rtc.h>
#include <ec/lenovo/h8/h8.h>
#include <delay.h>
#include "smi.h"
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler
*/
extern global_nvs_t *gnvs;
static void mainboard_smm_init(void)
{
printk(BIOS_DEBUG, "initializing SMI\n");
/* Enable 0x1600/0x1600 register pair */
ec_set_bit(0x00, 0x05);
}
int mainboard_io_trap_handler(int smif)
{
static int smm_initialized;
if (!smm_initialized) {
mainboard_smm_init();
smm_initialized = 1;
}
switch (smif) {
default:
return 0;
}
/* On success, the IO Trap Handler returns 1
* On failure, the IO Trap Handler returns a value != 1 */
return 1;
}
static void mainboard_smi_brightness_up(void)
{
u8 value;
if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
}
static void mainboard_smi_brightness_down(void)
{
u8 value;
if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,
(value - 0x10) & 0xf0);
}
static void mainboard_smi_handle_ec_sci(void)
{
u8 status = inb(EC_SC);
u8 event;
if (!(status & EC_SCI_EVT))
return;
event = ec_query();
printk(BIOS_DEBUG, "EC event %02x\n", event);
switch (event) {
case 0x14:
/* brightness up */
mainboard_smi_brightness_up();
break;
case 0x15:
/* brightness down */
mainboard_smi_brightness_down();
break;
default:
break;
}
}
void mainboard_smi_gpi(u32 gpi_sts)
{
if (gpi_sts & (1 << 12))
mainboard_smi_handle_ec_sci();
}
static int mainboard_finalized = 0;
int mainboard_smi_apmc(u8 data)
{
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
u8 tmp;
printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
data);
if (!pmbase)
return 0;
switch (data) {
case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600);
/* route H8SCI to SCI */
outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
tmp |= 0x02;
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
/* discard all events, and enable attention */
ec_write(0x80, 0x01);
break;
case APM_CNT_ACPI_DISABLE:
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */
ec_set_ports(0x66, 0x62);
/* route H8SCI# to SMI */
outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
tmp |= 0x01;
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
/* discard all events, and enable attention */
ec_write(0x80, 0x01);
break;
case APM_CNT_FINALIZE:
printk(BIOS_DEBUG, "APMC: FINALIZE\n");
if (mainboard_finalized) {
printk(BIOS_DEBUG, "APMC#: Already finalized\n");
return 0;
}
intel_me_finalize_smm();
intel_pch_finalize_smm();
intel_sandybridge_finalize_smm();
intel_model_206ax_finalize_smm();
mainboard_finalized = 1;
break;
default:
break;
}
return 0;
}

29
src/mainboard/lenovo/x230/thermal.h Normal file
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@ -0,0 +1,29 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef X230_THERMAL_H
#define X230_THERMAL_H
/* Temperature which OS will shutdown at */
#define CRITICAL_TEMPERATURE 100
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 90
#endif

10
src/southbridge/intel/bd82x6x/acpi/pcie.asl
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@ -155,6 +155,16 @@ Device (RP03)
{
Return (IRQM (RPPN))
}
#ifdef RP03_IS_EXPRESSCARD
Device (SLOT)
{
Name (_ADR, 0x00)
Method (_RMV, 0, NotSerialized)
{
Return (0x01)
}
}
#endif
}
Device (RP04)

6
src/southbridge/intel/bd82x6x/acpi/pcie_port.asl
View File

@ -27,4 +27,10 @@ Field (RPCS, AnyAcc, NoLock, Preserve)
Offset (0x4c), // Link Capabilities
, 24,
RPPN, 8, // Root Port Number
Offset (0x5A),
, 3,
PDC, 1,
Offset (0xDF),
, 6,
HPCS, 1,
}