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mb/google/brya/variants/kano: Init devicetree for kano 

Init basic override devicetree based on schematics

BUG=b:192370253
TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I283517427612e24eabe2ce736d677253065c7859
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
David Wu 2021-08-17 20:05:51 +08:00 committed by Tim Wawrzynczak
parent a56fffd645
commit e7f449386f
4 changed files with 465 additions and 1 deletions
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2
src/mainboard/google/brya/Kconfig.name
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@ -35,6 +35,8 @@ config BOARD_GOOGLE_REDRIX
config BOARD_GOOGLE_KANO config BOARD_GOOGLE_KANO
bool "-> Kano" bool "-> Kano"
select BOARD_GOOGLE_BASEBOARD_BRYA select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_I2C_MAX98373
select DRIVERS_I2C_NAU8825
config BOARD_GOOGLE_TAEKO config BOARD_GOOGLE_TAEKO
bool "-> Taeko" bool "-> Taeko"

2
src/mainboard/google/brya/variants/kano/Makefile.inc
View File

@ -2,3 +2,5 @@
bootblock-y += gpio.c bootblock-y += gpio.c
ramstage-y += gpio.c ramstage-y += gpio.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c

59
src/mainboard/google/brya/variants/kano/fw_config.c Normal file
View File

@ -0,0 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootstate.h>
#include <console/console.h>
#include <fw_config.h>
#include <gpio.h>
static const struct pad_config dmic_enable_pads[] = {
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC_CLK0_R */
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC_DATA0_R */
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC_CLK1_R */
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC_DATA1_R */
};
static const struct pad_config dmic_disable_pads[] = {
PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_S3, NONE),
PAD_NC(GPP_S6, NONE),
PAD_NC(GPP_S7, NONE),
};
static const struct pad_config i2s_enable_pads[] = {
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */
PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S_PCH_RX_SPKR_TX */
};
static const struct pad_config i2s_disable_pads[] = {
PAD_NC(GPP_R0, NONE),
PAD_NC(GPP_R1, NONE),
PAD_NC(GPP_R2, NONE),
PAD_NC(GPP_R3, NONE),
PAD_NC(GPP_R4, NONE),
PAD_NC(GPP_R5, NONE),
PAD_NC(GPP_R6, NONE),
PAD_NC(GPP_R7, NONE),
};
static void fw_config_handle(void *unused)
{
if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
return;
}
if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S))) {
printk(BIOS_INFO, "Configure audio over I2S with MAX98373 NAU88L25B.\n");
gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
}
}
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);

403
src/mainboard/google/brya/variants/kano/overridetree.cb
View File

@ -1,6 +1,407 @@
fw_config
field KB_BL 0 0
option KB_BL_ABSENT 0
option KB_BL_PRESENT 1
end
field AUDIO 1 3
option AUDIO_UNKNOWN 0
option MAX98373_NAU88L25B_I2S 1
end
end
chip soc/intel/alderlake chip soc/intel/alderlake
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI1 | Fingerprint MCU |
#| I2C0 | Audio |
#| I2C1 | Touchscreen |
#| I2C2 | SAR0 |
#| I2C3 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
device domain 0 on device domain 0 on
end device ref dtt on
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""DRAM""
register "options.tsr[1].desc" = ""Charger""
# TODO: below values are initial reference values only
## Active Policy
register "policies.active" = "{
[0] = {
.target = DPTF_CPU,
.thresholds = {
TEMP_PCT(85, 90),
TEMP_PCT(80, 80),
TEMP_PCT(75, 70),
}
}
}"
## Passive Policy
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
}"
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
}"
register "controls.power_limits" = "{
.pl1 = {
.min_power = 3000,
.max_power = 15000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,
},
.pl2 = {
.min_power = 55000,
.max_power = 55000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,
}
}"
## Charger Performance Control (Control, mA)
register "controls.charger_perf" = "{
[0] = { 255, 1700 },
[1] = { 24, 1500 },
[2] = { 16, 1000 },
[3] = { 8, 500 }
}"
## Fan Performance Control (Percent, Speed, Noise, Power)
register "controls.fan_perf" = "{
[0] = { 90, 6700, 220, 2200, },
[1] = { 80, 5800, 180, 1800, },
[2] = { 70, 5000, 145, 1450, },
[3] = { 60, 4900, 115, 1150, },
[4] = { 50, 3838, 90, 900, },
[5] = { 40, 2904, 55, 550, },
[6] = { 30, 2337, 30, 300, },
[7] = { 20, 1608, 15, 150, },
[8] = { 10, 800, 10, 100, },
[9] = { 0, 0, 0, 50, }
}"
## Fan options
register "options.fan.fine_grained_control" = "1"
register "options.fan.step_size" = "2"
device generic 0 on end
end
end
device ref ipu on end
device ref pcie4_0 on
# Enable CPU PCIE RP 1 using CLK 0
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_req = 0,
.clk_src = 0,
}"
end
device ref tcss_dma0 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
use tcss_usb3_port1 as dfp[0].typec_port
device generic 0 on end
end
end
device ref tcss_dma1 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
use tcss_usb3_port3 as dfp[0].typec_port
device generic 0 on end
end
end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref i2c0 on
chip drivers/i2c/nau8825
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
register "jkdet_enable" = "1"
register "jkdet_pull_enable" = "0"
register "jkdet_pull_up" = "0"
register "jkdet_polarity" = "1" # ActiveLow
register "vref_impedance" = "2" # 125kOhm
register "micbias_voltage" = "6" # 2.754
register "sar_threshold_num" = "4"
register "sar_threshold[0]" = "0x0C"
register "sar_threshold[1]" = "0x1C"
register "sar_threshold[2]" = "0x38"
register "sar_threshold[3]" = "0x60"
register "sar_hysteresis" = "1"
register "sar_voltage" = "6"
register "sar_compare_time" = "0" # 500ns
register "sar_sampling_time" = "0" # 2us
register "short_key_debounce" = "2" # 100ms
register "jack_insert_debounce" = "7" # 512ms
register "jack_eject_debounce" = "7" # 512ms
device i2c 1a on
probe AUDIO MAX98373_NAU88L25B_I2S
end
end
end #I2C0
device ref i2c1 on
chip drivers/i2c/hid
register "generic.hid" = ""ELAN90FC""
register "generic.desc" = ""ELAN Touchscreen""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
register "generic.reset_delay_ms" = "300"
register "generic.reset_off_delay_ms" = "1"
register "generic.enable_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "generic.enable_delay_ms" = "6"
register "generic.stop_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "generic.stop_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x10 on end
end
end
device ref i2c2 on
chip drivers/i2c/sx9324
register "desc" = ""SAR1 Proximity Sensor""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
register "speed" = "I2C_SPEED_FAST"
register "uid" = "1"
register "reg_gnrl_ctrl0" = "0x16"
register "reg_gnrl_ctrl1" = "0x21"
register "reg_afe_ctrl0" = "0x00"
register "reg_afe_ctrl1" = "0x10"
register "reg_afe_ctrl2" = "0x00"
register "reg_afe_ctrl3" = "0x00"
register "reg_afe_ctrl4" = "0x07"
register "reg_afe_ctrl5" = "0x00"
register "reg_afe_ctrl6" = "0x00"
register "reg_afe_ctrl7" = "0x07"
register "reg_afe_ctrl8" = "0x12"
register "reg_afe_ctrl9" = "0x0f"
register "reg_prox_ctrl0" = "0x12"
register "reg_prox_ctrl1" = "0x12"
register "reg_prox_ctrl2" = "0x90"
register "reg_prox_ctrl3" = "0x60"
register "reg_prox_ctrl4" = "0x0c"
register "reg_prox_ctrl5" = "0x12"
register "reg_prox_ctrl6" = "0x3c"
register "reg_prox_ctrl7" = "0x58"
register "reg_adv_ctrl0" = "0x00"
register "reg_adv_ctrl1" = "0x00"
register "reg_adv_ctrl2" = "0x00"
register "reg_adv_ctrl3" = "0x00"
register "reg_adv_ctrl4" = "0x00"
register "reg_adv_ctrl5" = "0x05"
register "reg_adv_ctrl6" = "0x00"
register "reg_adv_ctrl7" = "0x00"
register "reg_adv_ctrl8" = "0x00"
register "reg_adv_ctrl9" = "0x00"
register "reg_adv_ctrl10" = "0x5c"
register "reg_adv_ctrl11" = "0x52"
register "reg_adv_ctrl12" = "0xb5"
register "reg_adv_ctrl13" = "0x00"
register "reg_adv_ctrl14" = "0x80"
register "reg_adv_ctrl15" = "0x0c"
register "reg_adv_ctrl16" = "0x38"
register "reg_adv_ctrl17" = "0x56"
register "reg_adv_ctrl18" = "0x33"
register "reg_adv_ctrl19" = "0xf0"
register "reg_adv_ctrl20" = "0xf0"
device i2c 28 on end
end
chip drivers/i2c/sx9324
register "desc" = ""SAR2 Proximity Sensor""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
register "speed" = "I2C_SPEED_FAST"
register "uid" = "2"
register "reg_gnrl_ctrl0" = "0x16"
register "reg_gnrl_ctrl1" = "0x21"
register "reg_afe_ctrl0" = "0x00"
register "reg_afe_ctrl1" = "0x10"
register "reg_afe_ctrl2" = "0x00"
register "reg_afe_ctrl3" = "0x00"
register "reg_afe_ctrl4" = "0x07"
register "reg_afe_ctrl5" = "0x00"
register "reg_afe_ctrl6" = "0x00"
register "reg_afe_ctrl7" = "0x07"
register "reg_afe_ctrl8" = "0x12"
register "reg_afe_ctrl9" = "0x0f"
register "reg_prox_ctrl0" = "0x12"
register "reg_prox_ctrl1" = "0x12"
register "reg_prox_ctrl2" = "0x90"
register "reg_prox_ctrl3" = "0x60"
register "reg_prox_ctrl4" = "0x0c"
register "reg_prox_ctrl5" = "0x12"
register "reg_prox_ctrl6" = "0x3c"
register "reg_prox_ctrl7" = "0x58"
register "reg_adv_ctrl0" = "0x00"
register "reg_adv_ctrl1" = "0x00"
register "reg_adv_ctrl2" = "0x00"
register "reg_adv_ctrl3" = "0x00"
register "reg_adv_ctrl4" = "0x00"
register "reg_adv_ctrl5" = "0x05"
register "reg_adv_ctrl6" = "0x00"
register "reg_adv_ctrl7" = "0x00"
register "reg_adv_ctrl8" = "0x00"
register "reg_adv_ctrl9" = "0x00"
register "reg_adv_ctrl10" = "0x5c"
register "reg_adv_ctrl11" = "0x52"
register "reg_adv_ctrl12" = "0xb5"
register "reg_adv_ctrl13" = "0x00"
register "reg_adv_ctrl14" = "0x80"
register "reg_adv_ctrl15" = "0x0c"
register "reg_adv_ctrl16" = "0x38"
register "reg_adv_ctrl17" = "0x56"
register "reg_adv_ctrl18" = "0x33"
register "reg_adv_ctrl19" = "0xf0"
register "reg_adv_ctrl20" = "0xf0"
device i2c 2C on end
end
end
device ref i2c3 on end
device ref i2c5 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
register "wake" = "GPE0_DW2_14"
register "probed" = "1"
device i2c 15 on end
end
end
device ref hda on
chip drivers/i2c/max98373
register "vmon_slot_no" = "0"
register "imon_slot_no" = "1"
register "uid" = "0"
register "desc" = ""Right Speaker Amp""
register "name" = ""MAXR""
device i2c 31 on
probe AUDIO MAX98373_NAU88L25B_I2S
end
end
chip drivers/i2c/max98373
register "vmon_slot_no" = "2"
register "imon_slot_no" = "3"
register "uid" = "1"
register "desc" = ""Left Speaker Amp""
register "name" = ""MAXL""
device i2c 32 on
probe AUDIO MAX98373_NAU88L25B_I2S
end
end
end
device ref gspi1 on
chip drivers/spi/acpi
register "name" = ""CRFP""
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
register "wake" = "GPE0_DW2_15"
device spi 0 on end
end # FPMCU
end
device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]
use conn1 as mux_conn[1]
device pnp 0c09.0 on end
end
end
device ref pmc hidden
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
register "usb2_port_number" = "1"
register "usb3_port_number" = "1"
device generic 0 alias conn0 on end
end
chip drivers/intel/pmc_mux/conn
register "usb2_port_number" = "3"
register "usb3_port_number" = "3"
device generic 1 alias conn1 on end
end
end
end
end
device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C1 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(3, 1)"
device ref tcss_usb3_port3 on end
end
end
end
end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C1 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(3, 1)"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref usb2_port9 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
device ref usb2_port10 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref usb3_port1 on end
end
end
end
end
end
end end