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Add ddr3lv_support flag to pei_data structure 

This will enable DDR3 1.35V support for memory training in
the reference code.  It requires the board to be setup for
1.35V with whatever board-specific GPIOs are available.

Change-Id: I14e4686c20f9610f90678e6e3bece8ba80d8621a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1825
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Duncan Laurie 2012-07-11 10:40:45 -07:00 committed by Ronald G. Minnich
parent 53508fedf8
commit e8179b5138
1 changed files with 2 additions and 1 deletions
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3
src/northbridge/intel/sandybridge/pei_data.h
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@ -31,7 +31,7 @@
#define PEI_DATA_H #define PEI_DATA_H
typedef void (*tx_byte_func)(unsigned char byte); typedef void (*tx_byte_func)(unsigned char byte);
#define PEI_VERSION 2 #define PEI_VERSION 3
struct pei_data struct pei_data
{ {
uint32_t pei_version; uint32_t pei_version;
@ -98,6 +98,7 @@ struct pei_data
*/ */
uint8_t spd_data[4][256]; uint8_t spd_data[4][256];
tx_byte_func tx_byte; tx_byte_func tx_byte;
int ddr3lv_support;
} __attribute__((packed)); } __attribute__((packed));
#endif #endif