Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,

rename it slightly, make it visible only on relevant northbridges,
drop it entirely from via boards (as they seem to have picked it
up from AMD code without using it themselves), and make it
default to false for all boards.

Some romstages used to set this to "true" (ie. "print debug output"),
but I didn't follow up on it in Kconfig - if you need it to debug CAR,
enable it yourself.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-10-01 14:50:12 +00:00
parent f11b81d18d
commit e82618d037
32 changed files with 14 additions and 35 deletions

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@ -499,6 +499,16 @@ config DEBUG_RAM_SETUP
If unsure, say N.
config HAVE_DEBUG_CAR
def_bool n
config DEBUG_CAR
bool "Output verbose Cache-as-RAM debug messages"
default n
depends on HAVE_DEBUG_CAR
help
This option enables additional CAR related debug messages.
config DEBUG_PIRQ
bool "Check PIRQ table consistency"
default n

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@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1

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@ -2,7 +2,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1

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@ -1,5 +1,4 @@
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1

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@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1

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@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1

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@ -24,8 +24,6 @@
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
unsigned int get_sbdn(unsigned bus);
/* Used by raminit. */

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@ -24,8 +24,6 @@
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
unsigned int get_sbdn(unsigned bus);
/* Used by raminit. */

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@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1

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@ -25,7 +25,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1

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@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1

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@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1

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@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1

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@ -22,7 +22,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1

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@ -1,5 +1,4 @@
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1

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@ -1,5 +1,4 @@
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1

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@ -1,5 +1,4 @@
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1

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@ -23,7 +23,6 @@
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1

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@ -24,7 +24,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1 /* Used by RAM init. */
#define QRANK_DIMM_SUPPORT 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0

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@ -20,7 +20,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
// #define CACHE_AS_RAM_ADDRESS_DEBUG 1
// #define RAM_TIMING_DEBUG 1
// #define DQS_TRAIN_DEBUG 1
// #define RES_DEBUG 1

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@ -24,7 +24,6 @@
*/
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1

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@ -23,7 +23,6 @@
*/
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1

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@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1

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@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1

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@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1

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@ -23,7 +23,6 @@
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define SET_NB_CFG_54 1

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@ -23,7 +23,6 @@
*/
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define PAYLOAD_IS_SEABIOS 0
#include <stdint.h>

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@ -21,6 +21,7 @@ config NORTHBRIDGE_AMD_AMDFAM10
bool
select HAVE_DEBUG_RAM_SETUP
select HAVE_DEBUG_SMBUS
select HAVE_DEBUG_CAR
select HYPERTRANSPORT_PLUGIN_SUPPORT
select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
select MMCONF_SUPPORT

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@ -26,7 +26,7 @@
static inline void print_debug_addr(const char *str, void *val)
{
#if defined(CACHE_AS_RAM_ADDRESS_DEBUG) && CACHE_AS_RAM_ADDRESS_DEBUG == 1
#if CONFIG_DEBUG_CAR
printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
#endif
}

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@ -21,6 +21,7 @@ config NORTHBRIDGE_AMD_AMDK8
bool
select HAVE_DEBUG_RAM_SETUP
select HAVE_DEBUG_SMBUS
select HAVE_DEBUG_CAR
select HYPERTRANSPORT_PLUGIN_SUPPORT
config AGP_APERTURE_SIZE

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@ -3,13 +3,9 @@
*
*/
#ifndef CACHE_AS_RAM_ADDRESS_DEBUG
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#endif
static inline void print_debug_addr(const char *str, void *val)
{
#if CACHE_AS_RAM_ADDRESS_DEBUG == 1
#if CONFIG_DEBUG_CAR
printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
#endif
}

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@ -21,7 +21,6 @@
#define ASSEMBLY 1
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#include <stdint.h>
#include <device/pci_def.h>