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arch/mips: Add base MIPS architecture support 

Add the build infrastructure and basic architectural support required
to build for targets using the MIPS architecture. This is sufficient
to run on a simulator, but will require the addition of some cache
maintenance and timer setup in order to run on real hardware.

BUG=chrome-os-partner:31438, chromium:409082
TEST=none yet

Change-Id: I027902d8408e419b626d0aab7768bc564bd49047
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fcc0d934d7223922c878b1f87021cb5c2d7e6f21
Original-Change-Id: If4f99554463bd3760fc142477440326fd16c67cc
Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207972
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8760
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Paul Burton 2014-06-14 00:00:10 +01:00 committed by Patrick Georgi
parent cb8f36043c
commit e8530033b8
29 changed files with 1362 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Makefile.inc
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@ -70,7 +70,8 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
subdirs-y := src/lib src/console src/device src/ec src/southbridge src/soc
subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode
subdirs-y += util/cbfstool util/sconfig util/nvramtool
subdirs-y += src/arch/arm src/arch/arm64 src/arch/x86 src/arch/riscv
subdirs-y += src/arch/arm src/arch/arm64 src/arch/mips src/arch/riscv
subdirs-y += src/arch/x86
subdirs-y += src/mainboard/$(MAINBOARDDIR)
subdirs-y += site-local

5
src/Kconfig
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@ -277,10 +277,15 @@ config ARCH_RISCV
default n
select ANY_TOOLCHAIN
config ARCH_MIPS
bool
default n
source src/arch/x86/Kconfig
source src/arch/arm/Kconfig
source src/arch/arm64/Kconfig
source src/arch/riscv/Kconfig
source src/arch/mips/Kconfig
source src/vendorcode/Kconfig

37
src/arch/mips/Kconfig Normal file
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@ -0,0 +1,37 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2014 Imagination Technologies
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; version 2 of
# the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
# MA 02110-1301 USA
#
menu "Architecture (mips)"
config ARCH_BOOTBLOCK_MIPS
bool
default n
select ARCH_MIPS
config ARCH_ROMSTAGE_MIPS
bool
default n
config ARCH_RAMSTAGE_MIPS
bool
default n
endmenu

148
src/arch/mips/Makefile.inc Normal file
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@ -0,0 +1,148 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2014 Imagination Technologies
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; version 2 of
# the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
# MA 02110-1301 USA
#
###############################################################################
# MIPS specific options
###############################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y)
CBFSTOOL_PRE1_OPTS = -m mips -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET)
CBFSTOOL_PRE_OPTS = -b 0
endif
###############################################################################
# bootblock
###############################################################################
ifeq ($(CONFIG_ARCH_BOOTBLOCK_MIPS),y)
bootblock-y += boot.c
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c
bootblock-y += stages.c
bootblock-y += timer.c
bootblock-y += ../../lib/memcpy.c
bootblock-y += ../../lib/memmove.c
bootblock-y += ../../lib/memset.c
bootblock_lds = $(src)/arch/mips/bootblock.ld
bootblock_inc += $(src)/arch/mips/bootblock.inc
bootblock_inc += $(objgenerated)/bootblock.inc
# Much of the assembly code is generated by the compiler, and may contain
# terms which the preprocessor will happily go on to replace. For example
# "mips" would be replaced with "1". Clear all the built in definitions to
# prevent that.
bootblock-S-ccopts += -undef
$(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions
@printf " GEN $(subst $(obj)/,,$(@))\n"
printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@
$(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
@printf " GEN $(subst $(obj)/,,$(@))\n"
printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC_bootblock) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $@).disasm
$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC_bootblock) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E \
-I$(src)/include -I$(src)/arch/mips/include -I$(obj) \
-include $(obj)/build.h -include $(obj)/config.h -I. \
-I$(src) $< -o $@
$(objgenerated)/bootblock.inc: $(src)/arch/mips/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(obj)/config.h
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC_bootblock) $(bootblock-c-ccopts) $(CFLAGS_bootblock) -MM \
-MT$(objgenerated)/bootblock.inc \
$< > $(objgenerated)/bootblock.inc.d
$(CC_bootblock) $(bootblock-c-ccopts) -c -S $(CFLAGS_bootblock) -I. $< -o $@
$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(obj)/config.h
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(CC_bootblock) $(CFLAGS_bootblock) -nostdlib -Wl,--gc-sections -nostartfiles -include $(obj)/config.h -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(objgenerated)/bootblock.o $(bootblock-objs) -Wl,--end-group
endif # CONFIG_ARCH_BOOTBLOCK_MIPS
###############################################################################
# romstage
###############################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y)
romstage-y += boot.c
romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c
romstage-y += stages.c
romstage-y += timer.c
romstage-y += ../../lib/memcpy.c
romstage-y += ../../lib/memmove.c
romstage-y += ../../lib/memset.c
romstage-lds = $(src)/arch/mips/romstage.ld
$(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(CC_romstage) -nostdlib -Wl,--gc-sections -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage.ld -Wl,--start-group $(romstage-objs) -Wl,--end-group
$(objgenerated)/romstage.ld: $$(romstage-lds) $(obj)/ldoptions
@printf " GEN $(subst $(obj)/,,$(@))\n"
rm -f $@
printf '$(foreach ldscript,ldoptions $(romstage-lds),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp
mv $@.tmp $@
endif # CONFIG_ARCH_ROMSTAGE_MIPS
###############################################################################
# ramstage
###############################################################################
ifeq ($(CONFIG_ARCH_RAMSTAGE_MIPS),y)
ramstage-y += ashldi3.c
ramstage-y += boot.c
ramstage-y += stages.c
ramstage-y += tables.c
ramstage-y += timer.c
ramstage-y += ../../lib/memcpy.c
ramstage-y += ../../lib/memmove.c
ramstage-y += ../../lib/memset.c
ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
ramstage-lds = $(src)/arch/mips/ramstage.ld
$(objgenerated)/ramstage.ld: $$(ramstage-lds) $(obj)/ldoptions
@printf " GEN $(subst $(obj)/,,$(@))\n"
rm -f $@
printf '$(foreach ldscript,ldoptions $(ramstage-lds),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp
mv $@.tmp $@
$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(objgenerated)/ramstage.ld
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC_ramstage) -nostdlib -Wl,--gc-sections -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/ramstage.ld $<
$(objgenerated)/ramstage.o: $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -r -o $@ -Wl,--start-group $(ramstage-objs) -Wl,--end-group
endif # CONFIG_ARCH_RAMSTAGE_MIPS

27
src/arch/mips/boot.c Normal file
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@ -0,0 +1,27 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <arch/stages.h>
void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size)
{
printk(BIOS_SPEW, "entry = %p\n", entry);
stage_exit(entry);
}

44
src/arch/mips/bootblock.inc Normal file
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@ -0,0 +1,44 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
.set noreorder /* Prevent assembler from "optimizing" this code. */
.section ".start", "ax", %progbits
.globl _start
_start:
/* Set the stack pointer */
li $sp, CONFIG_STACK_TOP
/*
* Initialise the stack to a known value, used later to check for
* overflow.
*/
li $t0, CONFIG_STACK_BOTTOM
addi $t1, $sp, -4
li $t2, 0xdeadbeef
1: sw $t2, 0($t0)
bne $t0, $t1, 1b
addi $t0, $t0, 4
/* Run main */
b main
/* Should never return from main. */
2:
b 2b

57
src/arch/mips/bootblock.ld Normal file
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@ -0,0 +1,57 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2010 coresystems GmbH
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
OUTPUT_ARCH(mips)
ENTRY(_start)
PHDRS
{
to_load PT_LOAD;
}
preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;
SECTIONS
{
. = CONFIG_BOOTBLOCK_BASE;
/* This section might be better named .setup */
.rom : {
_rom = .;
*(.start);
*(.id);
*(.text);
*(.text.*);
*(.rom.text);
*(.rom.data);
*(.rom.data.*);
*(.rodata.*);
_erom = .;
} : to_load = 0xff
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
}
}

45
src/arch/mips/bootblock_simple.c Normal file
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@ -0,0 +1,45 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <arch/hlt.h>
#include <arch/stages.h>
#include <bootblock_common.h>
#include <cbfs.h>
#include <console/console.h>
void main(void)
{
const char *stage_name = "fallback/romstage";
void *entry;
bootblock_cpu_init();
bootblock_mainboard_init();
#if CONFIG_BOOTBLOCK_CONSOLE
console_init();
#endif
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
if (entry != (void *)-1)
stage_exit(entry);
hlt();
}

55
src/arch/mips/early_console.c Normal file
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@ -0,0 +1,55 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <console/console.h>
#include <console/vtxprintf.h>
void console_tx_byte(unsigned char byte)
{
if (byte == '\n')
console_tx_byte('\r');
#if CONFIG_CONSOLE_SERIAL_UART
uart_tx_byte(byte);
#endif
}
void console_tx_flush(void)
{
#if CONFIG_CONSOLE_SERIAL_UART
uart_tx_flush();
#endif
}
int do_printk(int msg_level, const char *fmt, ...)
{
va_list args;
int i;
if (msg_level > console_loglevel)
return 0;
va_start(args, fmt);
i = vtxprintf(console_tx_byte, fmt, args);
va_end(args);
console_tx_flush();
return i;
}

48
src/arch/mips/include/arch/byteorder.h Normal file
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@ -0,0 +1,48 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MIPS_ARCH_BYTEORDER_H
#define __MIPS_ARCH_BYTEORDER_H
#include <stdint.h>
#include <swab.h>
#ifndef __ORDER_LITTLE_ENDIAN__
#errror "What endian are you!?"
#endif
#define cpu_to_le64(x) ((uint64_t)(x))
#define le64_to_cpu(x) ((uint64_t)(x))
#define cpu_to_le32(x) ((uint32_t)(x))
#define le32_to_cpu(x) ((uint32_t)(x))
#define cpu_to_le16(x) ((uint16_t)(x))
#define le16_to_cpu(x) ((uint16_t)(x))
#define cpu_to_be64(x) swab64(x)
#define be64_to_cpu(x) swab64(x)
#define cpu_to_be32(x) swab32((x))
#define be32_to_cpu(x) swab32((x))
#define cpu_to_be16(x) swab16((x))
#define be16_to_cpu(x) swab16((x))
#define ntohll(x) be64_to_cpu(x)
#define htonll(x) cpu_to_be64(x)
#define ntohl(x) be32_to_cpu(x)
#define htonl(x) cpu_to_be32(x)
#endif /* __MIPS_ARCH_BYTEORDER_H */

23
src/arch/mips/include/arch/cache.h Normal file
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@ -0,0 +1,23 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MIPS_ARCH_CACHE_H
#define __MIPS_ARCH_CACHE_H
#endif /* __MIPS_ARCH_CACHE_H */

43
src/arch/mips/include/arch/cpu.h Normal file
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@ -0,0 +1,43 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MIPS_ARCH_CPU_H
#define __MIPS_ARCH_CPU_H
#define asmlinkage
#ifndef __PRE_RAM__
#include <device/device.h>
struct cpu_driver {
struct device_operations *ops;
struct cpu_device_id *id_table;
};
struct thread;
struct cpu_info {
device_t cpu;
unsigned long index;
};
#endif /* !__PRE_RAM__ */
#endif /* __MIPS_ARCH_CPU_H */

30
src/arch/mips/include/arch/early_variables.h Normal file
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@ -0,0 +1,30 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MIPS_ARCH_EARLY_VARIABLES_H
#define __MIPS_ARCH_EARLY_VARIABLES_H
#define CAR_GLOBAL
#define CAR_MIGRATE(migrate_fn_)
static inline void car_migrate_variables(void) {}
#define car_get_var(var) (var)
#define car_set_var(var, val) { (var) = (val); }
#endif /* __MIPS_ARCH_EARLY_VARIABLES_H */

25
src/arch/mips/include/arch/exception.h Normal file
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@ -0,0 +1,25 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MIPS_ARCH_EXCEPTION_H
#define __MIPS_ARCH_EXCEPTION_H
static inline void exception_init(void) {}
#endif /* __MIPS_ARCH_EXCEPTION_H */

29
src/arch/mips/include/arch/hlt.h Normal file
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@ -0,0 +1,29 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MIPS_ARCH_HLT_H
#define __MIPS_ARCH_HLT_H
static inline __attribute__((always_inline)) void hlt(void)
{
for (;;)
;
}
#endif /* __MIPS_ARCH_HLT_H */

125
src/arch/mips/include/arch/io.h Normal file
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@ -0,0 +1,125 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* Based on arch/armv7/include/arch/io.h:
* Copyright 2013 Google Inc.
* Copyright (C) 1996-2000 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MIPS_ARCH_IO_H
#define __MIPS_ARCH_IO_H
#include <types.h>
#include <arch/cache.h>
#include <arch/byteorder.h>
static inline uint8_t read8(unsigned long addr)
{
asm("sync");
return *(volatile uint8_t *)addr;
}
static inline uint16_t read16(unsigned long addr)
{
asm("sync");
return *(volatile uint16_t *)addr;
}
static inline uint32_t read32(unsigned long addr)
{
asm("sync");
return *(volatile uint32_t *)addr;
}
static inline void write8(unsigned long addr, uint8_t val)
{
asm("sync");
*(volatile uint8_t *)addr = val;
asm("sync");
}
static inline void write16(unsigned long addr, uint16_t val)
{
asm("sync");
*(volatile uint16_t *)addr = val;
asm("sync");
}
static inline void write32(unsigned long addr, uint32_t val)
{
asm("sync");
*(volatile uint32_t *)addr = val;
asm("sync");
}
/*
* Clear and set bits in one shot. These macros can be used to clear and
* set multiple bits in a register using a single call. These macros can
* also be used to set a multiple-bit bit pattern using a mask, by
* specifying the mask in the 'clear' parameter and the new bit pattern
* in the 'set' parameter.
*/
#define out_arch(type, endian, a, v) write##type(cpu_to_##endian(v), a)
#define in_arch(type, endian, a) endian##_to_cpu(read##type(a))
#define out_le32(a, v) out_arch(l, le32, a, v)
#define out_le16(a, v) out_arch(w, le16, a, v)
#define in_le32(a) in_arch(l, le32, a)
#define in_le16(a) in_arch(w, le16, a)
#define out_be32(a, v) out_arch(l, be32, a, v)
#define out_be16(a, v) out_arch(w, be16, a, v)
#define in_be32(a) in_arch(l, be32, a)
#define in_be16(a) in_arch(w, be16, a)
#define out_8(a, v) writeb(v, a)
#define in_8(a) readb(a)
#define clrbits(type, addr, clear) \
out_##type((addr), in_##type(addr) & ~(clear))
#define setbits(type, addr, set) \
out_##type((addr), in_##type(addr) | (set))
#define clrsetbits(type, addr, clear, set) \
out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
#define setbits_be32(addr, set) setbits(be32, addr, set)
#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
#define setbits_le32(addr, set) setbits(le32, addr, set)
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
#define setbits_be16(addr, set) setbits(be16, addr, set)
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
#define setbits_le16(addr, set) setbits(le16, addr, set)
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
#define clrbits_8(addr, clear) clrbits(8, addr, clear)
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
#endif /* __MIPS_ARCH_IO_H */

30
src/arch/mips/include/arch/pci_ops.h Normal file
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@ -0,0 +1,30 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef ARCH_MIPS_PCI_OPS_H
#define ARCH_MIPS_PCI_OPS_H
#include <stddef.h>
static inline const struct pci_bus_operations *pci_config_default(void)
{
return NULL;
}
#endif

29
src/arch/mips/include/arch/stages.h Normal file
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@ -0,0 +1,29 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MIPS_ARCH_STAGES_H
#define __MIPS_ARCH_STAGES_H
extern void main(void);
void stage_entry(void);
void stage_exit(void *);
void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size);
#endif /* __MIPS_ARCH_STAGES_H */

67
src/arch/mips/include/arch/types.h Normal file
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@ -0,0 +1,67 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* Based on src/arch/armv7/include/arch/types.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MIPS_ARCH_TYPES_H
#define __MIPS_ARCH_TYPES_H
typedef unsigned short umode_t;
/*
* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
* header files exported to user space
*/
typedef __signed__ char __s8;
typedef unsigned char __u8;
typedef __signed__ short __s16;
typedef unsigned short __u16;
typedef __signed__ int __s32;
typedef unsigned int __u32;
#if defined(__GNUC__)
__extension__ typedef __signed__ long long __s64;
__extension__ typedef unsigned long long __u64;
#endif
typedef signed char s8;
typedef unsigned char u8;
typedef signed short s16;
typedef unsigned short u16;
typedef signed int s32;
typedef unsigned int u32;
typedef signed long long s64;
typedef unsigned long long u64;
#define BITS_PER_LONG 32
/* Dma addresses are 32-bits wide. */
typedef u32 dma_addr_t;
typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t;
#endif /* __MIPS_ARCH_TYPES_H */

30
src/arch/mips/include/bootblock_common.h Normal file
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@ -0,0 +1,30 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifdef CONFIG_BOOTBLOCK_CPU_INIT
#include CONFIG_BOOTBLOCK_CPU_INIT
#endif
#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT
#include CONFIG_BOOTBLOCK_MAINBOARD_INIT
#else
static void bootblock_mainboard_init(void)
{
}
#endif

99
src/arch/mips/include/stdint.h Normal file
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@ -0,0 +1,99 @@
/*
* This file is part of the coreboot project.
*
* Based on src/arch/armv7/include/stdint.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MIPS_STDINT_H
#define __MIPS_STDINT_H
#if defined(__GNUC__)
#define __HAVE_LONG_LONG__ 1
#else
#define __HAVE_LONG_LONG__ 0
#endif
/* Exact integral types */
typedef unsigned char uint8_t;
typedef signed char int8_t;
typedef unsigned short uint16_t;
typedef signed short int16_t;
typedef unsigned int uint32_t;
typedef signed int int32_t;
#if __HAVE_LONG_LONG__
typedef unsigned long long uint64_t;
typedef signed long long int64_t;
#endif
/* Small types */
typedef unsigned char uint_least8_t;
typedef signed char int_least8_t;
typedef unsigned short uint_least16_t;
typedef signed short int_least16_t;
typedef unsigned int uint_least32_t;
typedef signed int int_least32_t;
#if __HAVE_LONG_LONG__
typedef unsigned long long uint_least64_t;
typedef signed long long int_least64_t;
#endif
/* Fast Types */
typedef unsigned char uint_fast8_t;
typedef signed char int_fast8_t;
typedef unsigned int uint_fast16_t;
typedef signed int int_fast16_t;
typedef unsigned int uint_fast32_t;
typedef signed int int_fast32_t;
#if __HAVE_LONG_LONG__
typedef unsigned long long uint_fast64_t;
typedef signed long long int_fast64_t;
#endif
/* Types for `void *' pointers. */
typedef int intptr_t;
typedef unsigned int uintptr_t;
/* Largest integral types */
#if __HAVE_LONG_LONG__
typedef long long int intmax_t;
typedef unsigned long long uintmax_t;
#else
typedef long int intmax_t;
typedef unsigned long int uintmax_t;
#endif
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
#if __HAVE_LONG_LONG__
typedef uint64_t u64;
#endif
typedef int8_t s8;
typedef int16_t s16;
typedef int32_t s32;
#undef __HAVE_LONG_LONG__
#endif /* __MIPS_STDINT_H */

121
src/arch/mips/ramstage.ld Normal file
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@ -0,0 +1,121 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* Based on src/arch/arm/ramstage.ld:
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
OUTPUT_ARCH(mips)
ENTRY(stage_entry)
PHDRS
{
to_load PT_LOAD;
}
SECTIONS
{
. = CONFIG_SYS_SDRAM_BASE;
.text : {
_text = .;
_start = .;
*(.text.stage_entry.mips);
*(.text);
*(.text.*);
. = ALIGN(16);
_etext = .;
} : to_load
.ctors : {
. = ALIGN(0x100);
__CTOR_LIST__ = .;
*(.ctors);
LONG(0);
__CTOR_END__ = .;
}
.rodata : {
_rodata = .;
. = ALIGN(4);
console_drivers = .;
KEEP(*(.rodata.console_drivers));
econsole_drivers = . ;
. = ALIGN(4);
pci_drivers = . ;
KEEP(*(.rodata.pci_driver));
epci_drivers = . ;
cpu_drivers = . ;
KEEP(*(.rodata.cpu_driver));
ecpu_drivers = . ;
_bs_init_begin = .;
KEEP(*(.bs_init));
_bs_init_end = .;
*(.rodata)
*(.rodata.*)
. = ALIGN(4);
_erodata = .;
}
.data : {
_data = .;
*(.data)
_edata = .;
}
/* bss will be cleared by cbfs_load_stage */
_bss = .;
.bss . : {
*(.bss)
*(.sbss)
*(COMMON)
}
_ebss = .;
_end = .;
/*
* coreboot from the perspective of the loader really "ends"
* here. Only symbols are placed after this.
*/
_heap = .;
_eheap = . + CONFIG_HEAP_SIZE;
_stack = CONFIG_STACK_BOTTOM;
_estack = CONFIG_STACK_TOP;
/*
* The ram segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
*/
_ram_seg = _text;
_eram_seg = _eheap;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.note.*)
}
}

72
src/arch/mips/romstage.ld Normal file
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@ -0,0 +1,72 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
OUTPUT_ARCH(mips)
ENTRY(stage_entry)
PHDRS
{
to_load PT_LOAD;
}
preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;
SECTIONS
{
. = CONFIG_ROMSTAGE_BASE;
.romtext . : {
_rom = .;
_start = .;
*(.text.stage_entry.mips);
*(.text.startup);
*(.text);
} : to_load
.romdata . : {
*(.rodata);
*(.data);
. = ALIGN(16);
_erom = .;
}
/* bss will be cleared by cbfs_load_stage */
.bss . : {
. = ALIGN(8);
_bss = .;
*(.bss)
*(.sbss)
*(COMMON)
}
_ebss = .;
_end = .;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.eh_frame);
}
}

35
src/arch/mips/stages.c Normal file
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@ -0,0 +1,35 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/stages.h>
#include <arch/cache.h>
__attribute__((section(".text.stage_entry.mips"))) void stage_entry(void)
{
main();
}
void stage_exit(void *addr)
{
void (*doit)(void) = addr;
/* TODO: synci */
doit();
}

67
src/arch/mips/tables.c Normal file
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@ -0,0 +1,67 @@
/*
* This file is part of the coreboot project.
*
* Based on src/arch/armv7/tables.c:
* Copyright (C) 2003 Eric Biederman
* Copyright (C) 2005 Steve Magnani
* Copyright (C) 2008-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <cpu/cpu.h>
#include <boot/tables.h>
#include <boot/coreboot_tables.h>
#include <string.h>
#include <cbmem.h>
#include <lib.h>
#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
void cbmem_arch_init(void)
{
}
struct lb_memory *write_tables(void)
{
unsigned long table_pointer, new_table_pointer;
post_code(0x9d);
table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE,
MAX_COREBOOT_TABLE_SIZE);
if (!table_pointer) {
printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n");
return NULL;
}
new_table_pointer = write_coreboot_table(0UL, 0UL, table_pointer,
table_pointer);
if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE))
printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n",
new_table_pointer - table_pointer,
MAX_COREBOOT_TABLE_SIZE);
printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
new_table_pointer - table_pointer);
post_code(0x9e);
/* Print CBMEM sections */
cbmem_list();
return get_lb_mem();
}

31
src/arch/mips/timer.c Normal file
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@ -0,0 +1,31 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <delay.h>
#include <timer.h>
void init_timer(void)
{
/* TODO */
}
void udelay(unsigned usec)
{
/* TODO */
}

1
src/cpu/Kconfig
View File

@ -9,6 +9,7 @@ source src/cpu/ti/Kconfig
source src/cpu/amd/Kconfig
source src/cpu/dmp/Kconfig
source src/cpu/intel/Kconfig
source src/cpu/mips/Kconfig
source src/cpu/via/Kconfig
source src/cpu/qemu-x86/Kconfig
source src/cpu/x86/Kconfig

36
src/cpu/mips/Kconfig Normal file
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@ -0,0 +1,36 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2014 Imagination Technologies
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; version 2 of
# the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
# MA 02110-1301 USA
#
config CPU_MIPS
bool
select ARCH_BOOTBLOCK_MIPS
select ARCH_ROMSTAGE_MIPS
select ARCH_RAMSTAGE_MIPS
config BOOTBLOCK_ROM_OFFSET
hex
depends on CPU_MIPS
default 0x00
config CBFS_HEADER_ROM_OFFSET
hex
depends on CPU_MIPS
default 0x10

2
toolchain.inc
View File

@ -64,7 +64,7 @@ CFLAGS_arm := -mno-unaligned-access -ffunction-sections -fdata-sections
CFLAGS_arm64 := -ffunction-sections -fdata-sections
CFLAGS_mipsel := -mips32r2 -G 0
CFLAGS_mipsel := -mips32r2 -G 0 -ffunction-sections -fdata-sections
CFLAGS_x86_32 := -ffunction-sections -fdata-sections