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armv7: update sync barrier usage in dcache_op_set_way() 

This moves the dsb() before the loop to sync any outstanding memory
accesses, and adds an isb() after the loop to ensure all outstanding
instructions are completed.

Change-Id: I1a11b39f104ae780370cfd2db3badcf4e91dc017
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2929
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
David Hendricks 2013-03-26 21:34:01 -07:00 committed by Stefan Reinauer
parent dc82fc5634
commit e85f4eb1b0
1 changed files with 3 additions and 2 deletions
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5
src/arch/armv7/lib/cache.c
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@ -111,6 +111,8 @@ static void dcache_op_set_way(enum dcache_op op)
/* FIXME: do we need to use CTR.DminLine here? */ /* FIXME: do we need to use CTR.DminLine here? */
linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4; linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4;
dsb();
/* /*
* Set/way operations require an interesting bit packing. See section * Set/way operations require an interesting bit packing. See section
* B4-35 in the ARMv7 Architecture Reference Manual: * B4-35 in the ARMv7 Architecture Reference Manual:
@ -144,8 +146,7 @@ static void dcache_op_set_way(enum dcache_op op)
} }
} }
} }
isb();
dsb();
} }
static void dcache_foreach(enum dcache_op op) static void dcache_foreach(enum dcache_op op)