From e874b1c1794406aa9adcd00a06cdb713b50b88ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 14 Oct 2020 19:17:35 +0200 Subject: [PATCH] cpu/intel/common: implement the two missing CPPC v2 autonomous registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This implements the two missing registers for the CPPC Hardware Autonomous mode (HWP) to the CPPC v2 package. The right values can be determined via Intel SDM and the ACPI 6.3 spec. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46463 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Menzel Reviewed-by: Matt Delco --- src/cpu/intel/common/common_init.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index d0b66d4815..3ea8f36ea8 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -239,11 +239,23 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) if (version >= 2) { /* Autonomous Selection Enable is populated below */ - /* Autonomous Activity Window Register */ - config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = unsupported; + msr.addrl = IA32_HWP_REQUEST; - /* Energy Performance Preference Register */ - config->regs[CPPC_PERF_PREF] = unsupported; + /* + * Autonomous Activity Window Register + * ResourceTemplate(){Register(FFixedHW, 0x0a, 0x20, 0x774, 0x04,)}, + */ + msr.bit_width = 10; + msr.bit_offset = 32; + config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = msr; + + /* + * Autonomous Energy Performance Preference Register + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x774, 0x04,)}, + */ + msr.bit_width = 8; + msr.bit_offset = 24; + config->regs[CPPC_PERF_PREF] = msr; /* Reference Performance */ config->regs[CPPC_REF_PERF] = unsupported;