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mb/google/brya/var/agah: Update FBVDD power-down delay 

The EEs have observed the ramp down delay on this signal in more detail
and 40 ms can still meet the sequencing requirements.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I49ef801f7a3fd7945ded63da1399eaf57fd6aef0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Tim Wawrzynczak 2022-06-30 15:57:05 -06:00 committed by Felix Held
parent 0e582862c8
commit e88989a5d4
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/google/brya/acpi/power.asl
View File

@ -173,7 +173,7 @@ Method (PGOF, 0, Serialized)
/* Ramp down FBVDD (active-low) and let rail discharge to <10% */
\_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN)
GPPL (GPIO_FBVDD_PG, 0, 20)
Sleep (150)
Sleep (40)
/* Ramp down PEXVDD and let rail discharge to <10% */
\_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN)

2
src/mainboard/google/brya/variants/agah/variant.c
View File

@ -56,7 +56,7 @@ static const struct power_rail_sequence gpu_on_seq[] = {
/* In GCOFF entry order (i.e., power-off order) */
static const struct power_rail_sequence gpu_off_seq[] = {
{ "FBVDD", FBVDD_PWR_EN, true, FBVDD_PG, 150,},
{ "FBVDD", FBVDD_PWR_EN, true, FBVDD_PG, 40,},
{ "PEXVDD", PEXVDD_PWR_EN, false, PEXVDD_PG, 10,},
{ "NVVDD+MSVDD", NVVDD_PWR_EN, false, NVVDD_PG, 2,},
{ "NV3_3", NV33_PWR_EN, false, NV33_PG, 4,},