vc/mediatek/mt8195: Remove unused code
Remove unused drivers and some fast calibration implementations to align with the latest MTK memory reference code. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I3b235cbceb231898f00fce7905f596eab54ca595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57275 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ryan Chuang
Hung-Te Lin
parent
d37aeb1bcb
commit
e895b2aa9d
File diff suppressed because it is too large
Load Diff
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@ -819,69 +819,6 @@ void DramcSWTxTracking(DRAMC_CTX_T *p)
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}
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}
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#endif
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#endif
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#if ENABLE_RX_TRACKING
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void DramcRxInputDelayTrackingInit_Common(DRAMC_CTX_T *p)
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{
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U8 ii, backup_rank;
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U32 u4WbrBackup = GetDramcBroadcast();
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backup_rank = u1GetRank(p);
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DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
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//Enable RX_FIFO macro DIV4 clock CG
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vIO32WriteFldAlign((DDRPHY_REG_MISC_CG_CTRL1), 0xffffffff, MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL);
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for (ii = RANK_0; ii < p->support_rank_num; ii++)
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{
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vSetRank(p, ii);
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//DVS mode to RG mode
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vIO32WriteFldAlign((DDRPHY_REG_RK_B0_RXDVS2), 0x0, RK_B0_RXDVS2_R_RK0_DVS_MODE_B0);
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vIO32WriteFldAlign((DDRPHY_REG_RK_B1_RXDVS2), 0x0, RK_B1_RXDVS2_R_RK0_DVS_MODE_B1);
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//Turn off F_DLY individual calibration option (CTO_AGENT_RDAT cannot separate DR/DF error)
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//tracking rising and update rising/falling together
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vIO32WriteFldAlign((DDRPHY_REG_RK_B0_RXDVS2), 0x1, RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0);
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vIO32WriteFldAlign((DDRPHY_REG_RK_B1_RXDVS2), 0x1, RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1);
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//DQ/DQM/DQS DLY MAX/MIN value under Tracking mode
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/* DQS, DQ, DQM (DQ, DQM are tied together now) -> controlled using DQM MAX_MIN */
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/* Byte 0 */
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vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS3), P_Fld(0x0, RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0) | P_Fld(0xff, RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0));
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vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS4), P_Fld(0x0, RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0) | P_Fld(0x1ff, RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0));
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/* Byte 1 */
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vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS3), P_Fld(0x0, RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1) | P_Fld(0xff, RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1));
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vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS4), P_Fld(0x0, RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1) | P_Fld(0x1ff, RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1));
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//Threshold for LEAD/LAG filter
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vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS1), P_Fld(0x0, RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD) | P_Fld(0x0, RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG));
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vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS1), P_Fld(0x0, RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD) | P_Fld(0x0, RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG));
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//DQ/DQS Rx DLY adjustment for tracking mode
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vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2), P_Fld(0x1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0) | P_Fld(0x1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0));
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vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2), P_Fld(0x1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1) | P_Fld(0x1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1));
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vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2), P_Fld(0x3, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0) | P_Fld(0x3, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0));
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vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2), P_Fld(0x3, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1) | P_Fld(0x3, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1));
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}
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vSetRank(p, backup_rank);
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//Tracking lead/lag counter >> Rx DLY adjustment fixed to 1
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vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x0, B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0);
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vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x0, B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1);
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//DQIEN pre-state option to block update for RX ASVA 1-2
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vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0);
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vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1);
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DramcBroadcastOnOff(u4WbrBackup);
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}
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#endif
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#if SIMULATION_RX_DVS || ENABLE_RX_TRACKING
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#if SIMULATION_RX_DVS || ENABLE_RX_TRACKING
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void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p)
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void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p)
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{
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{
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@ -974,76 +911,6 @@ void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p)
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}
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}
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#endif
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#endif
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#if ENABLE_RX_TRACKING
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void DramcRxInputDelayTrackingHW(DRAMC_CTX_T *p)
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{
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BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
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DRAM_CHANNEL_T channel_bak = p->channel;
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U8 ii, backup_rank;
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U32 u4WbrBackup = GetDramcBroadcast();
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DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
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vSetPHY2ChannelMapping(p, CHANNEL_A);
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backup_rank = u1GetRank(p);
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//Rx DLY tracking setting (Static)
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vIO32WriteFldMulti((DDRPHY_REG_B0_RXDVS0),
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P_Fld(1, B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0) |
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P_Fld(0, B0_RXDVS0_R_RX_RANKINCTL_B0) |
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P_Fld(1, B0_RXDVS0_R_RX_RANKINSEL_B0));
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vIO32WriteFldMulti((DDRPHY_REG_B1_RXDVS0),
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P_Fld(1, B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1) |
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P_Fld(0, B1_RXDVS0_R_RX_RANKINCTL_B1) |
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P_Fld(1, B1_RXDVS0_R_RX_RANKINSEL_B1));
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vIO32WriteFldMulti((DDRPHY_REG_B0_DQ9), P_Fld(0x1, B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0) | P_Fld(0, B0_DQ9_R_DMRXDVS_VALID_LAT_B0));
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vIO32WriteFldMulti((DDRPHY_REG_B1_DQ9), P_Fld(!isLP4_DSC, B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1) | P_Fld(0, B1_DQ9_R_DMRXDVS_VALID_LAT_B1));
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vIO32WriteFldMulti((DDRPHY_REG_CA_CMD9), P_Fld(isLP4_DSC, CA_CMD9_R_DMRXDVS_RDSEL_LAT_CA) | P_Fld(0, CA_CMD9_R_DMRXDVS_VALID_LAT_CA));
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//Rx DLY tracking function CG enable
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vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0);
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vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1);
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//Rx DLY tracking lead/lag counter enable
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vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0x1, B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0);
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vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0x1, B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1);
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#ifdef DPM_CONTROL_AFTERK
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vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 3, LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN);
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#endif
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//fra 0: origin mode (use LEAD/LAG rising tracking) 1: new mode (use LEAD/LAG rising/fall tracking, more faster)
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vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS1), 1, B0_RXDVS1_F_LEADLAG_TRACK_B0);
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vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS1), 1, B1_RXDVS1_F_LEADLAG_TRACK_B1);
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for (ii = RANK_0; ii < p->support_rank_num; ii++)
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{
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vSetRank(p, ii);
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//Rx DLY tracking update enable (HW mode)
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vIO32WriteFldMulti((DDRPHY_REG_RK_B0_RXDVS2),
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P_Fld(2, RK_B0_RXDVS2_R_RK0_DVS_MODE_B0) |
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P_Fld(1, RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0) |
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P_Fld(1, RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0));
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vIO32WriteFldMulti((DDRPHY_REG_RK_B1_RXDVS2),
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P_Fld(2, RK_B1_RXDVS2_R_RK0_DVS_MODE_B1) |
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P_Fld(1, RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1) |
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P_Fld(1, RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1));
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}
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vSetRank(p, backup_rank);
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//Rx DLY tracking: "TRACK_CLR" let rx_dly reload the correct dly setting
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vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 1, B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0);
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vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 1, B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1);
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vIO32WriteFldAlign((DDRPHY_REG_B0_RXDVS0), 0, B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0);
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vIO32WriteFldAlign((DDRPHY_REG_B1_RXDVS0), 0, B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1);
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DramcBroadcastOnOff(u4WbrBackup);
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}
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#endif
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///TODO: wait for porting +++
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///TODO: wait for porting +++
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#if __A60868_TO_BE_PORTING__
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#if __A60868_TO_BE_PORTING__
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#if RX_DLY_TRACK_ONLY_FOR_DEBUG
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#if RX_DLY_TRACK_ONLY_FOR_DEBUG
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@ -1201,111 +1068,6 @@ void DummyReadForDqsGatingRetryNonShuffle(DRAMC_CTX_T *p, bool bEn)
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#endif // __A60868_TO_BE_PORTING__
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#endif // __A60868_TO_BE_PORTING__
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#ifdef DUMMY_READ_FOR_TRACKING
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void DramcDummyReadAddressSetting(DRAMC_CTX_T *p)
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{
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U8 backup_channel = p->channel, backup_rank = p->rank;
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U8 channelIdx, rankIdx;
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dram_addr_t dram_addr;
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// for (channelIdx = CHANNEL_A; channelIdx < CHANNEL_NUM; channelIdx++)
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for (channelIdx = CHANNEL_A; channelIdx < p->support_channel_num; channelIdx++)
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{
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vSetPHY2ChannelMapping(p, channelIdx);
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for (rankIdx = RANK_0; rankIdx < RANK_MAX; rankIdx++)
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{
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vSetRank(p, rankIdx);
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dram_addr.ch = channelIdx;
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dram_addr.rk = rankIdx;
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get_dummy_read_addr(&dram_addr);
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mcSHOW_DBG_MSG3(("=== dummy read address: CH_%d, RK%d, row: 0x%x, bk: %d, col: 0x%x\n\n",
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channelIdx, rankIdx, dram_addr.row, dram_addr.bk, dram_addr.col));
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vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR2), P_Fld(dram_addr.row, RK_DUMMY_RD_ADR2_DMY_RD_ROW_ADR)
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| P_Fld(dram_addr.bk, RK_DUMMY_RD_ADR2_DMY_RD_BK));
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vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR), P_Fld(dram_addr.col, RK_DUMMY_RD_ADR_DMY_RD_COL_ADR)
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| P_Fld(0, RK_DUMMY_RD_ADR_DMY_RD_LEN));
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}
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}
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vSetPHY2ChannelMapping(p, backup_channel);
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vSetRank(p, backup_rank);
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}
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void DramcDummyReadForTrackingEnable(DRAMC_CTX_T *p)
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{
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U8 backup_rank = p->rank;
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U8 rankIdx;
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/* Dummy read pattern (Better efficiency during rx dly tracking) DE: YH Tsai, Wei-jen */
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for (rankIdx = RANK_0; rankIdx < p->support_rank_num; rankIdx++)
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{
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vSetRank(p, rankIdx);
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vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA0, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA0_DMY_RD_RK0_WDATA0
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vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA1, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA1_DMY_RD_RK0_WDATA1
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vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA2, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA2_DMY_RD_RK0_WDATA2
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vIO32Write4B_All(DRAMC_REG_RK_DUMMY_RD_WDATA3, 0xAAAA5555); // Field RK0_DUMMY_RD_WDATA3_DMY_RD_RK0_WDATA3
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}
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vSetRank(p, backup_rank);
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vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL);//Dummy Read rank selection is controlled by Test Agent
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#if 0//__ETT__
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/* indicate ROW_ADR = 2 for Dummy Write pattern address, in order to avoid pattern will be overwrited by MEM_TEST(test range 0xffff)
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* Pattern locates: 0x40010000, 0x40010100, 0x80010000, 0x80010100 */
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dram_addr_t dram_addr;
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dram_addr.ch = 0;
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dram_addr.rk = 0;
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get_dummy_read_addr(&dram_addr);
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vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_ADR), P_Fld(dram_addr.row, RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR)
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| P_Fld(dram_addr.col, RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR)
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| P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_LEN));
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vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_BK), dram_addr.bk, RK0_DUMMY_RD_BK_DMY_RD_RK0_BK);
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dram_addr.rk = 1;
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get_dummy_read_addr(&dram_addr);
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vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_ADR), P_Fld(dram_addr.row, RK1_DUMMY_RD_ADR_DMY_RD_RK1_ROW_ADR)
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| P_Fld(dram_addr.col, RK1_DUMMY_RD_ADR_DMY_RD_RK1_COL_ADR)
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| P_Fld(0, RK1_DUMMY_RD_ADR_DMY_RD_RK1_LEN));
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vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_BK), dram_addr.bk, RK1_DUMMY_RD_BK_DMY_RD_RK1_BK);
|
|
||||||
|
|
||||||
/* trigger dummy write pattern 0xAAAA5555 */
|
|
||||||
vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DMY_WR_DBG);
|
|
||||||
vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x0, DUMMY_RD_DMY_WR_DBG);
|
|
||||||
#else
|
|
||||||
DramcDummyReadAddressSetting(p);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* DUMMY_RD_RX_TRACK = 1:
|
|
||||||
* During "RX input delay tracking enable" and "DUMMY_RD_EN=1" Dummy read will force a read command to a certain rank,
|
|
||||||
* ignoring whether or not EMI has executed a read command to that certain rank in the past 4us.
|
|
||||||
*/
|
|
||||||
|
|
||||||
if (p->frequency >= 1600)
|
|
||||||
{
|
|
||||||
#ifdef DPM_CONTROL_AFTERK
|
|
||||||
vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1,
|
|
||||||
P_Fld(3, LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL) | P_Fld(3, LPIF_LOW_POWER_CFG_1_DMYRD_EN));
|
|
||||||
#endif
|
|
||||||
vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(1, DUMMY_RD_DMY_RD_RX_TRACK) | P_Fld(1, DUMMY_RD_DUMMY_RD_EN));
|
|
||||||
mcSHOW_DBG_MSG2(("High Freq DUMMY_READ_FOR_TRACKING: ON\n"));
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
mcSHOW_DBG_MSG2(("Low Freq DUMMY_READ_FOR_TRACKING: OFF\n"));
|
|
||||||
}
|
|
||||||
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef IMPEDANCE_HW_SAVING
|
#ifdef IMPEDANCE_HW_SAVING
|
||||||
void DramcImpedanceHWSaving(DRAMC_CTX_T *p)
|
void DramcImpedanceHWSaving(DRAMC_CTX_T *p)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue