sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLIT

Tree is inconsistent with the use of TCO register space offsets and
related preprocessor defines. The legacy space was offset from ACPI
PM base by 0x60, but this changed with later platforms. The convenient
way is to define the TCO registers relative to its base address and
subtract 0x60 here, but this change cannot be easily done tree-wide or
in one go.

For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until
all platforms use a clean style of tco_{read,write} accessor functions
instead of {read,write}_pmbase16(), or worse, inw/outl().

Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2022-11-19 18:39:22 +02:00
parent 560c3f5ccf
commit e8a3af1069
22 changed files with 45 additions and 0 deletions

View File

@ -34,6 +34,7 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_GMA_SWSMISCI select INTEL_GMA_SWSMISCI
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_HAS_L2_ENABLE_MSR select CPU_HAS_L2_ENABLE_MSR
select TCO_SPACE_NOT_YET_SPLIT
config VBOOT config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_MUST_REQUEST_DISPLAY

View File

@ -222,6 +222,8 @@
# define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ # define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
#define GPE_CTRL 0x40 #define GPE_CTRL 0x40
#define PM2A_CNT_BLK 0x50 #define PM2A_CNT_BLK 0x50
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
#define TCO_RLD 0x60 #define TCO_RLD 0x60
#define TCO_STS 0x64 #define TCO_STS 0x64
# define SECOND_TO_STS (1 << 17) # define SECOND_TO_STS (1 << 17)
@ -230,6 +232,7 @@
# define TCO_LOCK (1 << 12) # define TCO_LOCK (1 << 12)
# define TCO_TMR_HALT (1 << 11) # define TCO_TMR_HALT (1 << 11)
#define TCO_TMR 0x70 #define TCO_TMR 0x70
#endif
/* I/O ports */ /* I/O ports */
#define RST_CNT 0xcf9 #define RST_CNT 0xcf9

View File

@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
select NO_CBFS_MCACHE select NO_CBFS_MCACHE
select TCO_SPACE_NOT_YET_SPLIT
config DCACHE_BSP_STACK_SIZE config DCACHE_BSP_STACK_SIZE
hex hex

View File

@ -184,6 +184,8 @@
# define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ # define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
#define GPE_CTRL 0x40 #define GPE_CTRL 0x40
#define PM2A_CNT_BLK 0x50 #define PM2A_CNT_BLK 0x50
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
#define TCO_RLD 0x60 #define TCO_RLD 0x60
#define TCO_STS 0x64 #define TCO_STS 0x64
# define SECOND_TO_STS (1 << 17) # define SECOND_TO_STS (1 << 17)
@ -192,6 +194,7 @@
# define TCO_LOCK (1 << 12) # define TCO_LOCK (1 << 12)
# define TCO_TMR_HALT (1 << 11) # define TCO_TMR_HALT (1 << 11)
#define TCO_TMR 0x70 #define TCO_TMR 0x70
#endif
#if !defined(__ASSEMBLER__) && !defined(__ACPI__) #if !defined(__ASSEMBLER__) && !defined(__ACPI__)

View File

@ -12,6 +12,7 @@ config SOC_SPECIFIC_OPTIONS
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select MRC_SETTINGS_PROTECT select MRC_SETTINGS_PROTECT
select REG_SCRIPT select REG_SCRIPT
select TCO_SPACE_NOT_YET_SPLIT
config BROADWELL_LPDDR3 config BROADWELL_LPDDR3
bool bool

View File

@ -53,12 +53,15 @@
#define SWGPE_CTRL (1 << 1) #define SWGPE_CTRL (1 << 1)
#define DEVACT_STS 0x44 #define DEVACT_STS 0x44
#define PM2_CNT 0x50 #define PM2_CNT 0x50
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
#define TCO1_CNT 0x60 #define TCO1_CNT 0x60
#define TCO_TMR_HLT (1 << 11) #define TCO_TMR_HLT (1 << 11)
#define TCO1_STS 0x64 #define TCO1_STS 0x64
#define DMISCI_STS (1 << 9) #define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66 #define TCO2_STS 0x66
#define TCO2_STS_SECOND_TO (1 << 1) #define TCO2_STS_SECOND_TO (1 << 1)
#endif
#define GPE0_REG_MAX 4 #define GPE0_REG_MAX 4
#define GPE0_REG_SIZE 32 #define GPE0_REG_SIZE 32

View File

@ -23,6 +23,7 @@ config PCH_SPECIFIC_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select SPI_FLASH select SPI_FLASH
select TCO_SPACE_NOT_YET_SPLIT
config EHCI_BAR config EHCI_BAR
hex hex

View File

@ -36,6 +36,7 @@ config SOUTH_BRIDGE_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
select TCO_SPACE_NOT_YET_SPLIT
config EHCI_BAR config EHCI_BAR
hex hex

View File

@ -464,6 +464,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap);
#define PM2_CNT 0x50 // mobile only #define PM2_CNT 0x50 // mobile only
#define C3_RES 0x54 #define C3_RES 0x54
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
#define TCO1_STS 0x64 #define TCO1_STS 0x64
#define TCO1_TIMEOUT (1 << 3) #define TCO1_TIMEOUT (1 << 3)
#define DMISCI_STS (1 << 9) #define DMISCI_STS (1 << 9)
@ -473,6 +474,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap);
#define TCO_TMR_HLT (1 << 11) #define TCO_TMR_HLT (1 << 11)
#define TCO_LOCK (1 << 12) #define TCO_LOCK (1 << 12)
#define TCO2_CNT 0x6a #define TCO2_CNT 0x6a
#endif
#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */
#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */

View File

@ -103,6 +103,9 @@ config INTEL_CHIPSET_LOCKDOWN
and S3 resume (always done by coreboot). Select this to let coreboot and S3 resume (always done by coreboot). Select this to let coreboot
to do this on normal boot path. to do this on normal boot path.
config TCO_SPACE_NOT_YET_SPLIT
bool
config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
bool bool
depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE

View File

@ -104,6 +104,7 @@
#define GPE_CNTL 0x42 #define GPE_CNTL 0x42
#define DEVACT_STS 0x44 #define DEVACT_STS 0x44
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
#define TCO1_STS 0x64 #define TCO1_STS 0x64
#define DMISCI_STS (1 << 9) #define DMISCI_STS (1 << 9)
#define BOOT_STS (1 << 18) #define BOOT_STS (1 << 18)
@ -111,6 +112,7 @@
#define TCO1_CNT 0x68 #define TCO1_CNT 0x68
#define TCO_LOCK (1 << 12) #define TCO_LOCK (1 << 12)
#define TCO2_CNT 0x6a #define TCO2_CNT 0x6a
#endif
u16 get_pmbase(void); u16 get_pmbase(void);

View File

@ -3,7 +3,15 @@
#ifndef SOUTHBRIDGE_INTEL_COMMON_TCO_H #ifndef SOUTHBRIDGE_INTEL_COMMON_TCO_H
#define SOUTHBRIDGE_INTEL_COMMON_TCO_H #define SOUTHBRIDGE_INTEL_COMMON_TCO_H
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
/* Could get conflicting values. */
#undef TCO1_STS
#undef TCO2_STS
#undef TCO1_CNT
#endif
#define PMBASE_TCO_OFFSET 0x60 #define PMBASE_TCO_OFFSET 0x60
#define TCO1_STS 0x04 #define TCO1_STS 0x04
#define TCO1_TIMEOUT (1 << 3) #define TCO1_TIMEOUT (1 << 3)
#define TCO2_STS 0x06 #define TCO2_STS 0x06

View File

@ -13,6 +13,7 @@ config SOUTHBRIDGE_INTEL_I82801DX
select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select BOOT_DEVICE_NOT_SPI_FLASH select BOOT_DEVICE_NOT_SPI_FLASH
select TCO_SPACE_NOT_YET_SPLIT
if SOUTHBRIDGE_INTEL_I82801DX if SOUTHBRIDGE_INTEL_I82801DX

View File

@ -140,8 +140,10 @@ void i82801dx_lpc_setup(void);
#define DEVACT_STS 0x44 #define DEVACT_STS 0x44
#define SS_CNT 0x50 #define SS_CNT 0x50
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
/* TCO1 Control Register */ /* TCO1 Control Register */
#define TCO1_CNT 0x68 #define TCO1_CNT 0x68
#endif
#define GEN_PMCON_1 0xa0 #define GEN_PMCON_1 0xa0
#define GEN_PMCON_2 0xa2 #define GEN_PMCON_2 0xa2

View File

@ -22,6 +22,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RESET
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
select SOUTHBRIDGE_INTEL_COMMON_HPET select SOUTHBRIDGE_INTEL_COMMON_HPET
select TCO_SPACE_NOT_YET_SPLIT
if SOUTHBRIDGE_INTEL_I82801GX if SOUTHBRIDGE_INTEL_I82801GX

View File

@ -323,7 +323,10 @@ void ich7_setup_cir(void);
#define DEVACT_STS 0x44 #define DEVACT_STS 0x44
#define SS_CNT 0x50 #define SS_CNT 0x50
#define C3_RES 0x54 #define C3_RES 0x54
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
#define TCO1_CNT 0x68 #define TCO1_CNT 0x68
#endif
#endif /* __ACPI__ */ #endif /* __ACPI__ */
#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */

View File

@ -20,6 +20,7 @@ config SOUTHBRIDGE_INTEL_I82801IX
select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 if !BOARD_EMULATION_QEMU_X86_Q35
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select TCO_SPACE_NOT_YET_SPLIT
select USE_WATCHDOG_ON_BOOT select USE_WATCHDOG_ON_BOOT
if SOUTHBRIDGE_INTEL_I82801IX if SOUTHBRIDGE_INTEL_I82801IX

View File

@ -21,6 +21,7 @@ config SOUTHBRIDGE_INTEL_I82801JX
select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select TCO_SPACE_NOT_YET_SPLIT
select USE_WATCHDOG_ON_BOOT select USE_WATCHDOG_ON_BOOT
if SOUTHBRIDGE_INTEL_I82801JX if SOUTHBRIDGE_INTEL_I82801JX

View File

@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
select TCO_SPACE_NOT_YET_SPLIT
config EHCI_BAR config EHCI_BAR
hex hex

View File

@ -445,9 +445,11 @@ void pch_enable(struct device *dev);
#define PM2_CNT 0x50 // mobile only #define PM2_CNT 0x50 // mobile only
#define C3_RES 0x54 #define C3_RES 0x54
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
#define TCO1_STS 0x64 #define TCO1_STS 0x64
#define DMISCI_STS (1 << 9) #define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66 #define TCO2_STS 0x66
#endif
#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */
#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */

View File

@ -34,6 +34,7 @@ config SOUTH_BRIDGE_OPTIONS
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
select TCO_SPACE_NOT_YET_SPLIT
config INTEL_LYNXPOINT_LP config INTEL_LYNXPOINT_LP
bool bool

View File

@ -619,10 +619,13 @@ void mainboard_config_rcba(void);
#define PM2_CNT 0x50 // mobile only #define PM2_CNT 0x50 // mobile only
#define C3_RES 0x54 #define C3_RES 0x54
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
#define TCO1_STS 0x64 #define TCO1_STS 0x64
#define DMISCI_STS (1 << 9) #define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66 #define TCO2_STS 0x66
#define SECOND_TO_STS (1 << 1) #define SECOND_TO_STS (1 << 1)
#endif
#define ALT_GP_SMI_EN2 0x5c #define ALT_GP_SMI_EN2 0x5c
#define ALT_GP_SMI_STS2 0x5e #define ALT_GP_SMI_STS2 0x5e