From e8afb0ee92a5e532153d96de833e4a88589761de Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 22 Jun 2020 07:16:27 +0300 Subject: [PATCH] Revert "mb/pcengines/apu2: Update GPIO Reads & writes" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 87f9fc8584c980dc4c73667f4c88d71d0e447a0c. GPIO configuration is supposed to be abstracted using and the details of ACPMMIO GPIO bank hidden. This commit took it the opposite direction. Change-Id: Iacd80d1ca24c9d187ff2c8e68e57a609213bad08 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/42684 Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/pcengines/apu2/gpio_ftns.c | 16 ++++++++-------- src/mainboard/pcengines/apu2/gpio_ftns.h | 3 --- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index 7bf0bc9a53..c249c2da5c 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -12,11 +12,11 @@ static u32 gpio_read_wrapper(u32 iomux_gpio) u32 gpio = iomux_gpio << 2; if (gpio < 0x100) - return read32((void *)(ACPIMMIO_GPIO0_BASE + (gpio & 0xff))); + return gpio0_read32(gpio & 0xff); else if (gpio >= 0x100 && gpio < 0x200) - return read32((void *)(ACPIMMIO_GPIO1_BASE + (gpio & 0xff))); + return gpio1_read32(gpio & 0xff); else if (gpio >= 0x200 && gpio < 0x300) - return read32((void *)(ACPIMMIO_GPIO2_BASE + (gpio & 0xff))); + return gpio2_read32(gpio & 0xff); die("Invalid GPIO"); } @@ -26,11 +26,11 @@ static void gpio_write_wrapper(u32 iomux_gpio, u32 setting) u32 gpio = iomux_gpio << 2; if (gpio < 0x100) - write32((void *)(ACPIMMIO_GPIO0_BASE + (gpio & 0xff)), setting); + gpio0_write32(gpio & 0xff, setting); else if (gpio >= 0x100 && gpio < 0x200) - write32((void *)(ACPIMMIO_GPIO1_BASE + (gpio & 0xff)), setting); + gpio1_write32(gpio & 0xff, setting); else if (gpio >= 0x200 && gpio < 0x300) - write32((void *)(ACPIMMIO_GPIO2_BASE + (gpio & 0xff)), setting); + gpio2_write32(gpio & 0xff, setting); } void configure_gpio(u32 gpio, u8 iomux_ftn, u32 setting) @@ -70,9 +70,9 @@ int get_spd_offset(void) * One SPD file contains all 4 options, determine which index to * read here, then call into the standard routines. */ - if (read32((void *)(ACPIMMIO_GPIO1_BASE + 0x02)) & BIT0) + if (gpio1_read8(0x02) & BIT0) index |= BIT0; - if (read32((void *)(ACPIMMIO_GPIO1_BASE + 0x06)) & BIT0) + if (gpio1_read8(0x06) & BIT0) index |= BIT1; return index; diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index a0ce03c672..d1e76de029 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -8,9 +8,6 @@ u8 read_gpio(u32 gpio); void write_gpio(u32 gpio, u8 value); int get_spd_offset(void); -#define ACPIMMIO_GPIO0_BASE 0xfed81500 -#define ACPIMMIO_GPIO1_BASE 0xfed81600 -#define ACPIMMIO_GPIO2_BASE 0xfed81700 // // Based on PC Engines APU2C and APU3A schematics // http://www.pcengines.ch/schema/apu2c.pdf