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mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp

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This patch configures FSP UPD values for HPD and DDC of DDI ports for
CMLRVP.

BUG=none
TEST= Tested that eDP works on CMLRVP.

Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
V Sowmya 2019-04-02 18:55:15 +05:30 committed by Patrick Georgi
parent c10fed0743
commit e8c655dd1b
1 changed files with 13 additions and 0 deletions
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13
src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
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@ -10,6 +10,19 @@ chip soc/intel/cannonlake
register "HeciEnabled" = "1"
register "s0ix_enable" = "1"
# Enable eDP device
register "DdiPortEdp" = "1"
# Enable HPD for DDI ports B/C
register "DdiPortBHpd" = "1"
register "DdiPortCHpd" = "1"
register "DdiPortDHpd" = "1"
register "DdiPortFHpd" = "1"
# Enable DDC for DDI ports B/C
register "DdiPortBDdc" = "1"
register "DdiPortCDdc" = "1"
register "DdiPortDDdc" = "1"
register "DdiPortFDdc" = "1"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,