sc7180: Add display support for mipi panels
- configure TROGDOR_HAS_MIPI_PANEL to "n" by default, it can be updated for mipi panels. - add simple rm69299 panel as an example to append new mipi panels. - use existing edid struct to update mipi panel parameters. - add dsi command tx interface for mipi panel on commands. Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52662 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Vinod Polimera
Julius Werner
parent
8ca68cf2ae
commit
e8cd480046
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@ -12,6 +12,10 @@ config TROGDOR_HAS_BRIDGE_BACKLIGHT
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default y if BOARD_GOOGLE_HOMESTAR
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default n
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config TROGDOR_HAS_MIPI_PANEL
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bool
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default n
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config TROGDOR_HAS_FINGERPRINT
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bool
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default y if BOARD_GOOGLE_COACHZ
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@ -15,6 +15,7 @@ romstage-y += boardid.c
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romstage-y += chromeos.c
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ramstage-y += mainboard.c
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ramstage-y += panel_driver.c
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ifneq ($(CONFIG_BOARD_GOOGLE_BUBS),y)
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ramstage-y += reset.c
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endif
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@ -12,6 +12,7 @@
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#include <soc/qupv3_config.h>
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#include <soc/qupv3_i2c.h>
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#include <soc/usb.h>
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#include <types.h>
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#include "board.h"
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@ -74,39 +75,52 @@ static void configure_display(void)
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gpio_output(GPIO_EN_PP3300_DX_EDP, 1);
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}
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static void display_init(struct edid *edid)
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static enum cb_err display_init(struct edid *edid, const struct panel_data *pinfo)
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{
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uint32_t dsi_bpp = 24;
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uint32_t lanes = 4;
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uint32_t lanes = pinfo ? pinfo->lanes : 4;
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if (mdss_dsi_config(edid, lanes, dsi_bpp))
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return;
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return CB_ERR;
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if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) {
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if (mdss_dsi_panel_initialize(pinfo))
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return CB_ERR;
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} else {
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sn65dsi86_bridge_configure(BRIDGE_BUS, BRIDGE_CHIP, edid, lanes, dsi_bpp);
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}
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sn65dsi86_bridge_configure(BRIDGE_BUS, BRIDGE_CHIP, edid, lanes, dsi_bpp);
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if (CONFIG(TROGDOR_HAS_BRIDGE_BACKLIGHT))
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sn65dsi86_backlight_enable(BRIDGE_BUS, BRIDGE_CHIP);
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mdp_dsi_video_config(edid);
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mdss_dsi_video_mode_config(edid, dsi_bpp);
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mdp_dsi_video_on();
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return CB_SUCCESS;
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}
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static void display_startup(void)
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{
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static struct edid ed;
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enum dp_pll_clk_src ref_clk = SN65_SEL_19MHZ;
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const struct panel_data *pinfo = NULL;
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i2c_init(QUPV3_0_SE2, I2C_SPEED_FAST); /* EDP Bridge I2C */
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if (display_init_required()) {
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configure_display();
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mdelay(250); /* Delay for the panel to be up */
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sn65dsi86_bridge_init(BRIDGE_BUS, BRIDGE_CHIP, ref_clk);
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if (sn65dsi86_bridge_read_edid(BRIDGE_BUS, BRIDGE_CHIP, &ed) < 0)
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return;
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if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) {
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pinfo = get_panel_config(&ed);
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} else {
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i2c_init(QUPV3_0_SE2, I2C_SPEED_FAST); /* EDP Bridge I2C */
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configure_display();
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mdelay(250); /* Delay for the panel to be up */
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sn65dsi86_bridge_init(BRIDGE_BUS, BRIDGE_CHIP, ref_clk);
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if (sn65dsi86_bridge_read_edid(BRIDGE_BUS, BRIDGE_CHIP, &ed) < 0)
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return;
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}
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printk(BIOS_INFO, "display init!\n");
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display_init(&ed);
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fb_new_framebuffer_info_from_edid(&ed, (uintptr_t)0);
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if (display_init(&ed, pinfo) == CB_SUCCESS)
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fb_new_framebuffer_info_from_edid(&ed, (uintptr_t)0);
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} else
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printk(BIOS_INFO, "Skipping display init.\n");
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}
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@ -0,0 +1,45 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <edid.h>
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#include <string.h>
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#include <types.h>
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#include <soc/display/mipi_dsi.h>
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#include <soc/display/panel.h>
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struct mipi_dsi_cmd visionox_init_cmds[] = {
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{{0xFE, 0x00, 0x15, 0x80}, 0x4, 0},
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{{0xc2, 0x08, 0x15, 0x80}, 0x4, 0},
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{{0x35, 0x00, 0x15, 0x80}, 0x4, 0},
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{{0x51, 0xff, 0x15, 0x80}, 0x4, 0},
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{{0x11, 0x00, 0x05, 0x80}, 0x4, 150000},
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{{0x29, 0x00, 0x05, 0x80}, 0x4, 50000},
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};
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static const struct edid visionox_edid = {
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.ascii_string = "RM69299",
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.manufacturer_name = "RM",
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.panel_bits_per_color = 8,
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.panel_bits_per_pixel = 24,
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.mode = {
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.pixel_clock = 158695,
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.lvds_dual_channel = 0,
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.refresh = 60,
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.ha = 1080, .hbl = 64, .hso = 26, .hspw = 2,
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.va = 2248, .vbl = 64, .vso = 56, .vspw = 4,
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.phsync = '-', .pvsync = '-',
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.x_mm = 74, .y_mm = 131,
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},
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};
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const struct panel_data panel_info = {
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.lanes = 4,
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.init_cmd = visionox_init_cmds,
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.init_cmd_count = 6,
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};
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const struct panel_data *get_panel_config(struct edid *edid)
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{
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memcpy(edid, &visionox_edid, sizeof(struct edid));
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edid_set_framebuffer_bits_per_pixel(edid, 32, 0);
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return &panel_info;
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}
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@ -2,10 +2,15 @@
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#include <device/mmio.h>
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#include <console/console.h>
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#include <assert.h>
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#include <edid.h>
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#include <delay.h>
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#include <symbols.h>
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#include <types.h>
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#include <soc/display/mdssreg.h>
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#include <string.h>
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#include <soc/display/mipi_dsi.h>
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#include <soc/display/panel.h>
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#include <soc/display/mdssreg.h>
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#include <soc/display/dsi_phy.h>
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#define DSI_DMA_STREAM1 0x0
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@ -17,6 +22,7 @@
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#define DSI_WC1 0x0
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#define DSI_EOF_BLLP_PWR 0x9
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#define DSI_DMA_TRIGGER_SEL 0x4
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#define TRAFFIC_MODE 0x1
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#define DSI_EN 0x1
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#define DSI_CLKLN_EN 0x1
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@ -24,6 +30,11 @@
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#define HS_TX_TO 0xEA60
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#define TIMER_RESOLUTION 0x4
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#define DSI_PAYLOAD_BYTE_BOUND 8
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#define DSI_PAYLOAD_SIZE_ALIGN 4
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#define DSI_CMD_DMA_TPG_EN BIT(1)
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#define DSI_TPG_DMA_FIFO_MODE BIT(2)
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#define DSI_CMD_DMA_PATTERN_SEL (BIT(16) | BIT(17))
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static void mdss_dsi_host_init(int num_of_lanes)
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{
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@ -55,11 +66,13 @@ static void mdss_dsi_host_init(int num_of_lanes)
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*/
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ctrl_mode |= BIT(1);
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mdss_dsi_clock_config();
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write32(&dsi0->trig_ctrl, DSI_DMA_STREAM1 << 8 | DSI_DMA_TRIGGER_SEL);
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write32(&dsi0->ctrl, dlnx_en << 4 | ctrl_mode);
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write32(&dsi0->cmd_mode_dma_ctrl,
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DSI_EMBED_MODE1 << 28 | DSI_POWER_MODE2 << 26 |
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DSI_PACK_TYPE1 << 24 | DSI_VC1 << 22 | DSI_DT1 << 16 | DSI_WC1);
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DSI_EMBED_MODE1 << 28 | DSI_POWER_MODE2 << 26 |
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DSI_PACK_TYPE1 << 24 | DSI_VC1 << 22 | DSI_DT1 << 16 | DSI_WC1);
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write32(&dsi0->eot_packet_ctrl, 0x1);
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}
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static void mdss_dsi_reset(void)
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@ -106,8 +119,6 @@ void mdss_dsi_video_mode_config(struct edid *edid, uint32_t bpp)
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vfp = edid->mode.vso;
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vbp = edid->mode.vbl - edid->mode.vso;
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mdss_dsi_clock_config();
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write32(&dsi0->video_mode_active_h,
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((edid->mode.ha + hbp) << 16) |
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hbp);
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@ -121,12 +132,12 @@ void mdss_dsi_video_mode_config(struct edid *edid, uint32_t bpp)
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(edid->mode.ha + hfp +
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hbp - 1));
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write32(&dsi0->video_mode_active_hsync, (edid->mode.hspw << 16) | 0);
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write32(&dsi0->video_mode_active_hsync, (edid->mode.hspw << 16));
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write32(&dsi0->video_mode_active_vsync, 0x0);
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write32(&dsi0->video_mode_active_vsync_vpos, edid->mode.vspw << 16 | 0);
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write32(&dsi0->video_mode_active_vsync_vpos, edid->mode.vspw << 16);
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write32(&dsi0->video_mode_ctrl,
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DSI_EOF_BLLP_PWR << 12 | dst_format << 4);
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DSI_EOF_BLLP_PWR << 12 | dst_format << 4 | TRAFFIC_MODE << 8);
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write32(&dsi0->hs_timer_ctrl, HS_TX_TO | TIMER_RESOLUTION << 16);
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@ -153,9 +164,132 @@ void mdss_dsi_clock_config(void)
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setbits32(&dsi0->clk_ctrl, DSI_AHBM_SCLK_ON | DSI_FORCE_ON_DYN_AHBM_HCLK);
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/* Clock for MDP/DSI, for DMA out from MDP */
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setbits32(&dsi0->clk_ctrl, DSI_FORCE_ON_DYN_AHBM_HCLK);
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setbits32(&dsi0->clk_ctrl, DSI_PCLK_ON);
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/* Clock for rest of DSI */
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setbits32(&dsi0->clk_ctrl, DSI_AHBS_HCLK_ON | DSI_DSICLK_ON |
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DSI_BYTECLK_ON | DSI_ESCCLK_ON);
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}
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static void mdss_dsi_set_intr(void)
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{
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write32(&dsi0->int_ctrl, 0x0);
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/* Enable all HW interrupts. */
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setbits32(&dsi0->int_ctrl, DSI_CMD_MODE_DMA_DONE_MASK | DSI_CMD_MODE_MDP_DONE_MASK |
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DSI_VIDEO_MODE_DONE_MASK | DSI_ERROR_MASK | DSI_BTA_DONE_MASK);
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}
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static int mdss_dsi_cmd_dma_trigger_for_panel(void)
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{
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uint32_t read_value;
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uint32_t count = 0;
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int status = 0;
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mdss_dsi_set_intr();
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write32(&dsi0->cmd_mode_dma_sw_trigger, 0x1);
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dsb();
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read_value = read32(&dsi0->int_ctrl) & 0x1;
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while (read_value != 0x1) {
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read_value = read32(&dsi0->int_ctrl) & 0x1;
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count++;
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if (count > 0xffff) {
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status = -1;
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printk(BIOS_ERR,
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"Panel CMD: count :%d command mode dma test failed\n", count);
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printk(BIOS_ERR,
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"Panel CMD: read value = %x, addr=%p\n",
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read_value, (&dsi0->int_ctrl));
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return status;
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}
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}
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write32(&dsi0->int_ctrl, (read32(&dsi0->int_ctrl) | 0x01000001));
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return status;
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}
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static int mdss_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count)
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{
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struct mipi_dsi_cmd *cm;
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uint8_t *pload = _dma_coherent;
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uint32_t size;
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int data = 0;
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int ret = 0;
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uint32_t *bp = NULL;
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cm = cmds;
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for (int i = 0; i < count; i++) {
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/* The payload size has to be a multiple of 4 */
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size = ALIGN_UP(cm->size, DSI_PAYLOAD_SIZE_ALIGN);
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assert(size < DSI_PAYLOAD_BYTE_BOUND);
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memcpy(pload, (cm[i].payload), size);
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bp = (uint32_t *)pload;
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/* Enable custom pattern stored in TPG DMA FIFO */
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data = DSI_CMD_DMA_PATTERN_SEL;
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/* select CMD_DMA_FIFO_MODE to 1 */
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data |= DSI_TPG_DMA_FIFO_MODE;
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data |= DSI_CMD_DMA_TPG_EN;
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write32(&dsi0->test_pattern_gen_ctrl, data);
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for (int j = 0; j < size; j += 4) {
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write32(&dsi0->test_pattern_gen_cmd_dma_init_val, *bp);
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bp++;
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}
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if ((size % 8) != 0)
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write32(&dsi0->test_pattern_gen_cmd_dma_init_val, 0x0);
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write32(&dsi0->dma_cmd_length, size);
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write32(&dsi0->cmd_mode_dma_sw_trigger, 0x1);
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ret += mdss_dsi_cmd_dma_trigger_for_panel();
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/* Reset the DMA TPG FIFO */
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write32(&dsi0->tpg_dma_fifo_reset, 0x1);
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write32(&dsi0->tpg_dma_fifo_reset, 0x0);
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/* Disable CMD_DMA_TPG */
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write32(&dsi0->test_pattern_gen_ctrl, 0x0);
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if (cm[i].delay_us)
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udelay(cm[i].delay_us);
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else
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udelay(80);
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}
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return ret;
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}
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static void mdss_dsi_clear_intr(void)
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{
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write32(&dsi0->int_ctrl, 0x0);
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/* Clear all the hardware interrupts */
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setbits32(&dsi0->int_ctrl, DSI_CMD_MODE_DMA_DONE_AK | DSI_CMD_MODE_MDP_DONE_AK |
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DSI_VIDEO_MODE_DONE_AK | DSI_BTA_DONE_AK | DSI_ERROR_AK);
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write32(&dsi0->err_int_mask0, 0x13FF3BFF);
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}
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int mdss_dsi_panel_initialize(const struct panel_data *pinfo)
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{
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int status = 0;
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uint32_t ctrl_mode = 0;
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struct mipi_dsi_cmd *cmds;
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assert((pinfo != NULL) && (pinfo->init_cmd != NULL));
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cmds = pinfo->init_cmd;
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ctrl_mode = read32(&dsi0->ctrl);
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/* Enable command mode before sending the commands */
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write32(&dsi0->ctrl, ctrl_mode | 0x04);
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status = mdss_dsi_cmds_tx(cmds, pinfo->init_cmd_count);
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write32(&dsi0->ctrl, ctrl_mode);
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mdss_dsi_clear_intr();
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return status;
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}
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@ -3,6 +3,7 @@
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#ifndef _SOC_DISPLAY_MIPI_DSI_H_
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#define _SOC_DISPLAY_MIPI_DSI_H_
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#include <soc/display/panel.h>
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/**********************************************************
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DSI register configuration options
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**********************************************************/
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@ -14,6 +15,12 @@
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#define DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2
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#define DSI_VIDEO_DST_FORMAT_RGB888 3
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struct mipi_dsi_cmd {
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char payload[4];
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uint32_t size;
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int delay_us;
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};
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enum {
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DSI_VIDEO_MODE,
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DSI_CMD_MODE,
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@ -21,7 +28,7 @@ enum {
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enum cb_err mdss_dsi_config(struct edid *edid, uint32_t num_of_lanes, uint32_t bpp);
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void mdss_dsi_clock_config(void);
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void mdss_dsi_video_mode_config(struct edid *edid,
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uint32_t bpp);
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void mdss_dsi_video_mode_config(struct edid *edid, uint32_t bpp);
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int mdss_dsi_panel_initialize(const struct panel_data *pinfo);
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#endif
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@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _PANEL_H_
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#define _PANEL_H_
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#include <types.h>
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struct panel_data {
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uint8_t lanes;
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struct mipi_dsi_cmd *init_cmd;
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uint32_t init_cmd_count;
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};
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void panel_power_on(void);
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const struct panel_data *get_panel_config(struct edid *edid);
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#endif /*_PANEL_H_ */
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