southbridge/intel/bd82x6x: Use common gpio.c
Use shared gpio code from common folder. Bd82x6x's gpio.c and gpio.h is used by other southbridges as well and will be removed once it is unused. Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13614 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
parent
ffc31d07f7
commit
e8e66f4763
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@ -12,7 +12,7 @@
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#include "northbridge/intel/sandybridge/sandybridge.h"
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#include "northbridge/intel/sandybridge/raminit_native.h"
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#include "southbridge/intel/bd82x6x/pch.h"
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#include "southbridge/intel/bd82x6x/gpio.h"
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#include <southbridge/intel/common/gpio.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cbfs.h>
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@ -1,4 +1,4 @@
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#include "southbridge/intel/bd82x6x/gpio.h"
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#include <southbridge/intel/common/gpio.h>
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const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO,
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.gpio1 = GPIO_MODE_GPIO,
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@ -1,4 +1,4 @@
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#include "southbridge/intel/bd82x6x/gpio.h"
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#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_NATIVE,
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.gpio1 = GPIO_MODE_NATIVE,
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@ -29,7 +29,7 @@
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <southbridge/intel/common/gpio.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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@ -1,4 +1,4 @@
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#include "southbridge/intel/bd82x6x/gpio.h"
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#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_NATIVE,
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.gpio1 = GPIO_MODE_NATIVE,
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@ -29,7 +29,7 @@
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <southbridge/intel/common/gpio.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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@ -21,6 +21,7 @@
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#include <device/pci.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <ec/quanta/ene_kb3940q/ec.h>
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#include "ec.h"
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@ -29,9 +30,6 @@
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#define FORCE_RECOVERY_MODE 0
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#define FORCE_DEVELOPER_MODE 0
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int get_pch_gpio(unsigned char gpio_num);
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#ifndef __PRE_RAM__
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#include <boot/coreboot_tables.h>
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@ -92,38 +90,9 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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}
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#endif
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int get_pch_gpio(unsigned char gpio_num)
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{
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device_t dev;
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int retval = 0;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 0);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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#endif
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u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe;
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if (!gpio_base)
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return(0);
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if (gpio_num >= 64){
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u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
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retval = ((gp_lvl3 >> (gpio_num - 64)) & 1);
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} else if (gpio_num >= 32){
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u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
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retval = ((gp_lvl2 >> (gpio_num - 32)) & 1);
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} else {
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u32 gp_lvl = inl(gpio_base + GP_LVL);
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retval = ((gp_lvl >> gpio_num) & 1);
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}
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return retval;
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}
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int get_write_protect_state(void)
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{
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return !get_pch_gpio(WP_GPIO);
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return !get_gpio(WP_GPIO);
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}
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int get_lid_switch(void)
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@ -141,7 +110,7 @@ int get_developer_mode_switch(void)
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#endif
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/* Servo GPIO is active low, reverse it for intial state (request) */
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dev_mode = !get_pch_gpio(DEVMODE_GPIO);
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dev_mode = !get_gpio(DEVMODE_GPIO);
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printk(BIOS_DEBUG,"DEVELOPER MODE FROM GPIO %d: %x\n",DEVMODE_GPIO,
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dev_mode);
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@ -13,7 +13,7 @@
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* GNU General Public License for more details.
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*/
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#include "southbridge/intel/bd82x6x/gpio.h"
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#include <southbridge/intel/common/gpio.h>
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const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_NONE, /* Unused */
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@ -30,7 +30,7 @@
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <southbridge/intel/common/gpio.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <halt.h>
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@ -19,6 +19,7 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include "ec.h"
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#include <ec/google/chromeec/ec.h>
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@ -73,21 +74,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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int get_write_protect_state(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 0);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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#endif
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u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
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//u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
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if (!gpio_base)
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return -1;
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u32 gp_lvl2 = inl(gpio_base + 0x38);
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return (gp_lvl2 >> (57 - 32)) & 1;
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return get_gpio(57);
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}
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int get_lid_switch(void)
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@ -16,7 +16,7 @@
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#ifndef LINK_GPIO_H
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#define LINK_GPIO_H
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#include "southbridge/intel/bd82x6x/gpio.h"
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#include <southbridge/intel/common/gpio.h>
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const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
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@ -32,6 +32,7 @@
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#include "onboard.h"
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#include "ec.h"
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <smbios.h>
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#include <device/pci.h>
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#include <ec/google/chromeec/ec.h>
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@ -30,8 +30,7 @@
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include "ec/google/chromeec/ec.h"
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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@ -21,6 +21,7 @@
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#include <device/pci.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <ec/compal/ene932/ec.h>
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#include "ec.h"
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int get_lid_switch(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 0);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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#endif
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u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
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if (!gpio_base)
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return 0;
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u32 gp_lvl = inl(gpio_base + GP_LVL);
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return (gp_lvl >> 15) & 1;
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return get_gpio(15);
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}
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int get_developer_mode_switch(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 0);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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#endif
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u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
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if (!gpio_base)
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return(0);
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/*
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* Dev mode is controled by EC and uboot stores a flag in TPM. This GPIO is only
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* for the debug header. It is AND'd to the EC request.
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u8 gpio = !get_gpio(17);
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/*
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* Dev mode is controlled by EC and uboot stores a flag in TPM.
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* This GPIO is only for the debug header.
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* It is AND'd to the EC request.
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*/
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u32 gp_lvl = inl(gpio_base + GP_LVL);
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printk(BIOS_DEBUG,"DEV MODE GPIO 17: %x\n", !((gp_lvl >> 17) & 1));
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printk(BIOS_DEBUG, "DEV MODE GPIO 17: %x\n", gpio);
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/* GPIO17, active low -- return active high reading and let
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* it be inverted by the caller if needed. */
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return !((gp_lvl >> 17) & 1);
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return gpio;
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}
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int get_write_protect_state(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 0);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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#endif
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u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
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if (!gpio_base)
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return 0;
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u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
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return !((gp_lvl3 >> (70 - 64)) & 1);
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return !get_gpio(70);
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}
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int get_recovery_mode_switch(void)
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{
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u8 rec_mode;
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 0);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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#endif
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u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
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if (!gpio_base)
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return(0);
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u8 gpio = !get_gpio(68);
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/* GPIO68, active low. For Servo support
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* Treat as active high and let the caller invert if needed. */
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u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
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rec_mode = !((gp_lvl3 >> (68 - 64)) & 1);
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printk(BIOS_DEBUG,"REC MODE GPIO 68: %x\n", rec_mode);
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printk(BIOS_DEBUG, "REC MODE GPIO 68: %x\n", gpio);
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return (rec_mode);
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return gpio;
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}
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int parrot_ec_running_ro(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 0);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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#endif
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u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
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if (!gpio_base)
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return(0);
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/* GPIO68 EC_RW is active low.
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* Treat as active high and let the caller invert if needed. */
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u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
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return !((gp_lvl3 >> (68 - 64)) & 1);
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return !get_gpio(68);
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}
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#ifndef PARROT_GPIO_H
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#define PARROT_GPIO_H
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#include "southbridge/intel/bd82x6x/gpio.h"
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#include <southbridge/intel/common/gpio.h>
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const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_NONE, /* NOT USED */
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <halt.h>
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#include <device/pci.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include "ec.h"
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#include <ec/quanta/it8518/ec.h>
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int get_write_protect_state(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 0);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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#endif
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u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
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if (!gpio_base)
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return 0;
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u32 gp_lvl = inl(gpio_base + GP_LVL);
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return !((gp_lvl >> 7) & 1);
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return !get_gpio(7);
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}
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int get_lid_switch(void)
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#ifndef STOUT_GPIO_H
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#define STOUT_GPIO_H
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#include "southbridge/intel/bd82x6x/gpio.h"
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#include <southbridge/intel/common/gpio.h>
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const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO, /* GPIO0 */
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <halt.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#ifndef __PRE_RAM__
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#include <boot/coreboot_tables.h>
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int get_developer_mode_switch(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 0);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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#endif
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u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
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u32 gp_lvl2 = inl(gpio_base + 0x38);
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/* Developer: GPIO17, active high */
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return (gp_lvl2 >> (57-32)) & 1;
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/* Developer: GPIO57, active high */
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return get_gpio(57);
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}
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int get_recovery_mode_switch(void)
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{
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device_t dev;
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#ifdef __PRE_RAM__
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dev = PCI_DEV(0, 0x1f, 0);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
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#endif
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u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
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u32 gp_lvl = inl(gpio_base + 0x0c);
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/* Recovery: GPIO22, active low */
|
||||
return !((gp_lvl >> 22) & 1);
|
||||
return !get_gpio(22);
|
||||
}
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
#ifndef EMERALDLAKE2_GPIO_H
|
||||
#define EMERALDLAKE2_GPIO_H
|
||||
|
||||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
|
|
|
@ -31,6 +31,7 @@
|
|||
#include <northbridge/intel/sandybridge/raminit.h>
|
||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <halt.h>
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
#ifndef KTQM77_GPIO_H
|
||||
#define KTQM77_GPIO_H
|
||||
|
||||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
/*
|
||||
* TODO: Investigate somehow... Current values are taken from a running
|
||||
|
|
|
@ -30,6 +30,7 @@
|
|||
#include <northbridge/intel/sandybridge/raminit.h>
|
||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <halt.h>
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO, // -USB30_SMIB - input
|
||||
.gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
#ifndef T520_GPIO_H
|
||||
#define T520_GPIO_H
|
||||
|
||||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO, // -USB30_SMI - input
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
#include <northbridge/intel/sandybridge/sandybridge.h>
|
||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <southbridge/intel/bd82x6x/gpio.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cbfs.h>
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
#ifndef LENOVO_X201_GPIO_H
|
||||
#define LENOVO_X201_GPIO_H
|
||||
|
||||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
|
|
|
@ -29,7 +29,7 @@
|
|||
#include <northbridge/intel/sandybridge/sandybridge.h>
|
||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <southbridge/intel/bd82x6x/gpio.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
|
||||
|
|
|
@ -17,7 +17,7 @@
|
|||
#ifndef X230_GPIO_H
|
||||
#define X230_GPIO_H
|
||||
|
||||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
#include <northbridge/intel/sandybridge/sandybridge.h>
|
||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <southbridge/intel/bd82x6x/gpio.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cbfs.h>
|
||||
|
|
|
@ -20,6 +20,7 @@
|
|||
#include <device/pci.h>
|
||||
#include <northbridge/intel/sandybridge/sandybridge.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
#define GPIO_SPI_WP 24
|
||||
#define GPIO_REC_MODE 42
|
||||
|
@ -119,19 +120,16 @@ int get_recovery_mode_switch(void)
|
|||
void init_bootmode_straps(void)
|
||||
{
|
||||
#ifdef __PRE_RAM__
|
||||
u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
|
||||
u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
|
||||
u32 gp_lvl = inl(gpio_base + GP_LVL);
|
||||
u32 flags = 0;
|
||||
|
||||
/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */
|
||||
if (gp_lvl & (1 << GPIO_SPI_WP))
|
||||
if (get_gpio(GPIO_SPI_WP))
|
||||
flags |= (1 << FLAG_SPI_WP);
|
||||
/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
|
||||
if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32))))
|
||||
if (!get_gpio(GPIO_REC_MODE))
|
||||
flags |= (1 << FLAG_REC_MODE);
|
||||
/* Developer: GPIO17 = KBC3_DVP_MODE, active high */
|
||||
if (gp_lvl & (1 << GPIO_DEV_MODE))
|
||||
if (get_gpio(GPIO_DEV_MODE))
|
||||
flags |= (1 << FLAG_DEV_MODE);
|
||||
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
#ifndef LUMPY_GPIO_H
|
||||
#define LUMPY_GPIO_H
|
||||
|
||||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
/*
|
||||
* GPIO SET 1 includes GPIO0 to GPIO31
|
||||
|
|
|
@ -33,6 +33,7 @@
|
|||
#include <northbridge/intel/sandybridge/raminit.h>
|
||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <halt.h>
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
#define GPIO_SPI_WP 68
|
||||
#define GPIO_REC_MODE 42
|
||||
|
@ -116,20 +117,16 @@ int get_recovery_mode_switch(void)
|
|||
void init_bootmode_straps(void)
|
||||
{
|
||||
#ifdef __PRE_RAM__
|
||||
u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
|
||||
u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
|
||||
u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
|
||||
u32 gp_lvl = inl(gpio_base + GP_LVL);
|
||||
u32 flags = 0;
|
||||
|
||||
/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */
|
||||
if (gp_lvl3 & (1 << (GPIO_SPI_WP-64)))
|
||||
if (get_gpio(GPIO_SPI_WP))
|
||||
flags |= (1 << FLAG_SPI_WP);
|
||||
/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
|
||||
if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32))))
|
||||
if (!get_gpio(GPIO_REC_MODE))
|
||||
flags |= (1 << FLAG_REC_MODE);
|
||||
/* Developer: GPIO17 = KBC3_DVP_MODE, active high */
|
||||
if (gp_lvl & (1 << GPIO_DEV_MODE))
|
||||
if (get_gpio(GPIO_DEV_MODE))
|
||||
flags |= (1 << FLAG_DEV_MODE);
|
||||
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
#ifndef STUMPY_GPIO_H
|
||||
#define STUMPY_GPIO_H
|
||||
|
||||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
/*
|
||||
* GPIO SET 1 includes GPIO0 to GPIO31
|
||||
|
|
|
@ -33,6 +33,7 @@
|
|||
#include <northbridge/intel/sandybridge/raminit.h>
|
||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <halt.h>
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
#include <tpm.h>
|
||||
#include <northbridge/intel/sandybridge/chip.h>
|
||||
#include "southbridge/intel/bd82x6x/pch.h"
|
||||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static void early_pch_init(void)
|
||||
{
|
||||
|
|
|
@ -35,6 +35,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
|
|||
select COMMON_FADT
|
||||
select ACPI_SATA_GENERATOR
|
||||
select HAVE_INTEL_FIRMWARE
|
||||
select SOUTHBRIDGE_INTEL_COMMON_GPIO
|
||||
|
||||
config EHCI_BAR
|
||||
hex
|
||||
|
|
|
@ -41,7 +41,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c
|
|||
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
|
||||
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
|
||||
|
||||
romstage-y += early_smbus.c me_status.c gpio.c
|
||||
romstage-y += early_smbus.c me_status.c
|
||||
romstage-y += reset.c
|
||||
romstage-y += early_spi.c early_pch_common.c
|
||||
romstage-y += early_rcba.c
|
||||
|
|
|
@ -18,6 +18,22 @@
|
|||
|
||||
#include <stdint.h>
|
||||
|
||||
/* ICH7 GPIOBASE */
|
||||
#define GPIO_USE_SEL 0x00
|
||||
#define GP_IO_SEL 0x04
|
||||
#define GP_LVL 0x0c
|
||||
#define GPO_BLINK 0x18
|
||||
#define GPI_INV 0x2c
|
||||
#define GPIO_USE_SEL2 0x30
|
||||
#define GP_IO_SEL2 0x34
|
||||
#define GP_LVL2 0x38
|
||||
#define GPIO_USE_SEL3 0x40
|
||||
#define GP_IO_SEL3 0x44
|
||||
#define GP_LVL3 0x48
|
||||
#define GP_RST_SEL1 0x60
|
||||
#define GP_RST_SEL2 0x64
|
||||
#define GP_RST_SEL3 0x68
|
||||
|
||||
#define GPIO_MODE_NATIVE 0
|
||||
#define GPIO_MODE_GPIO 1
|
||||
#define GPIO_MODE_NONE 1
|
||||
|
|
|
@ -462,22 +462,6 @@ early_usb_init (const struct southbridge_usb_port *portmap);
|
|||
#define XUSB2PRM 0xd4 /* 32bit */
|
||||
#define USB3PRM 0xdc /* 32bit */
|
||||
|
||||
/* ICH7 GPIOBASE */
|
||||
#define GPIO_USE_SEL 0x00
|
||||
#define GP_IO_SEL 0x04
|
||||
#define GP_LVL 0x0c
|
||||
#define GPO_BLINK 0x18
|
||||
#define GPI_INV 0x2c
|
||||
#define GPIO_USE_SEL2 0x30
|
||||
#define GP_IO_SEL2 0x34
|
||||
#define GP_LVL2 0x38
|
||||
#define GPIO_USE_SEL3 0x40
|
||||
#define GP_IO_SEL3 0x44
|
||||
#define GP_LVL3 0x48
|
||||
#define GP_RST_SEL1 0x60
|
||||
#define GP_RST_SEL2 0x64
|
||||
#define GP_RST_SEL3 0x68
|
||||
|
||||
/* ICH7 PMBASE */
|
||||
#define PM1_STS 0x00
|
||||
#define WAK_STS (1 << 15)
|
||||
|
|
|
@ -30,6 +30,7 @@
|
|||
#include <northbridge/intel/sandybridge/sandybridge.h>
|
||||
#include <arch/pci_mmio_cfg.h>
|
||||
#include <southbridge/intel/bd82x6x/me.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <cpu/intel/model_206ax/model_206ax.h>
|
||||
|
||||
/* While we read PMBASE dynamically in case it changed, let's
|
||||
|
|
Loading…
Reference in New Issue