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mb/google/var/vell: Add gpios to lock 

Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.

BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
vell boots successfully to kernel.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0c39d06e3b2f39db88d924205786bfa1b27df3fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Eric Lai 2022-02-08 11:42:13 +08:00 committed by Felix Held
parent 4c6f074e0b
commit e8f5c20282
1 changed files with 11 additions and 11 deletions
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22
src/mainboard/google/brya/variants/vell/gpio.c
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@ -11,19 +11,19 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_A11, NONE), PAD_NC(GPP_A11, NONE),
/* B2 : VRALERT# ==> RGB_RST_ODL */ /* B2 : VRALERT# ==> RGB_RST_ODL */
PAD_CFG_GPO(GPP_B2, 1, DEEP), PAD_CFG_GPO_LOCK(GPP_B2, 1, LOCK_CONFIG),
/* B15 : TIME_SYNC0 ==> NC */ /* B15 : TIME_SYNC0 ==> NC */
PAD_NC(GPP_B15, NONE), PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
/* C3 : SML0CLK ==> NC */ /* C3 : SML0CLK ==> NC */
PAD_NC(GPP_C3, NONE), PAD_NC(GPP_C3, NONE),
/* D3 : ISH_GP3 ==> EN_PP3300_SSD */ /* D3 : ISH_GP3 ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_D3, 1, DEEP), PAD_CFG_GPO_LOCK(GPP_D3, 1, LOCK_CONFIG),
/* D11 : ISH_SPI_MISO ==> USB_C3_LSX_TX */ /* D11 : ISH_SPI_MISO ==> USB_C3_LSX_TX */
PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4), PAD_CFG_NF_LOCK(GPP_D11, NONE, NF4, LOCK_CONFIG),
/* D12 : ISH_SPI_MOSI ==> USB_C3_LSX_RX_STRAP */ /* D12 : ISH_SPI_MOSI ==> USB_C3_LSX_RX_STRAP */
PAD_CFG_NF(GPP_D12, NONE, DEEP, NF4), PAD_CFG_NF_LOCK(GPP_D12, NONE, NF4, LOCK_CONFIG),
/* E3 : PROC_GP0 ==> MEM_STRAP_0 */ /* E3 : PROC_GP0 ==> MEM_STRAP_0 */
PAD_CFG_GPI(GPP_E3, NONE, DEEP), PAD_CFG_GPI(GPP_E3, NONE, DEEP),
@ -32,13 +32,13 @@ static const struct pad_config override_gpio_table[] = {
/* E7 : PROC_GP1 ==> MEM_STRAP_3 */ /* E7 : PROC_GP1 ==> MEM_STRAP_3 */
PAD_CFG_GPI(GPP_E7, NONE, DEEP), PAD_CFG_GPI(GPP_E7, NONE, DEEP),
/* E10 : THC0_SPI1_CS# ==> UWB_GSPI0_CS */ /* E10 : THC0_SPI1_CS# ==> UWB_GSPI0_CS */
PAD_CFG_NF(GPP_E10, NONE, DEEP, NF2), PAD_CFG_NF_LOCK(GPP_E10, NONE, NF2, LOCK_CONFIG),
/* E11 : THC0_SPI1_CLK ==> UWB_CLK */ /* E11 : THC0_SPI1_CLK ==> UWB_CLK */
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), PAD_CFG_NF_LOCK(GPP_E11, NONE, NF2, LOCK_CONFIG),
/* E12 : THC0_SPI1_IO1 ==> UWB_GSPI0_DI */ /* E12 : THC0_SPI1_IO1 ==> UWB_GSPI0_DI */
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3), PAD_CFG_NF_LOCK(GPP_E12, NONE, NF3, LOCK_CONFIG),
/* E13 : THC0_SPI1_IO2 ==> UWB_GSPI0_DO */ /* E13 : THC0_SPI1_IO2 ==> UWB_GSPI0_DO */
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3), PAD_CFG_NF_LOCK(GPP_E13, NONE, NF3, LOCK_CONFIG),
/* E22 : DDPA_CTRLCLK ==> WWAN_CONFIG0 */ /* E22 : DDPA_CTRLCLK ==> WWAN_CONFIG0 */
PAD_CFG_GPI(GPP_E22, NONE, DEEP), PAD_CFG_GPI(GPP_E22, NONE, DEEP),
/* E23 : DDPA_CTRLDATA ==> USB_C3_OC_ODL */ /* E23 : DDPA_CTRLDATA ==> USB_C3_OC_ODL */
@ -52,9 +52,9 @@ static const struct pad_config override_gpio_table[] = {
/* H7 : IC1_SCL ==> PCH_I2C_TPM_SCL */ /* H7 : IC1_SCL ==> PCH_I2C_TPM_SCL */
PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
/* H12 : I2C7_SDA ==> UWB_SDA */ /* H12 : I2C7_SDA ==> UWB_SDA */
PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), PAD_CFG_NF_LOCK(GPP_H12, NONE, NF1, LOCK_CONFIG),
/* H13 : I2C7_SCL ==> UWB_SCL */ /* H13 : I2C7_SCL ==> UWB_SCL */
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), PAD_CFG_NF_LOCK(GPP_H13, NONE, NF1, LOCK_CONFIG),
/* H15 : DDPB_CTRLCLK ==> USB_C3_AUX_DC_P */ /* H15 : DDPB_CTRLCLK ==> USB_C3_AUX_DC_P */
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF6), PAD_CFG_NF(GPP_H15, NONE, DEEP, NF6),
/* H17 : DDPB_CTRLDATA ==> USB_C3_AUX_DC_N */ /* H17 : DDPB_CTRLDATA ==> USB_C3_AUX_DC_N */