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superio/winbond: Improve code formatting 

Change-Id: Ia63e21b957d89690f36929f9ffbe8a7bf8f0e84c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS 2020-03-30 16:47:28 +02:00 committed by Felix Held
parent 4c0432ae65
commit e8fcf1bf8d
5 changed files with 116 additions and 116 deletions
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8
src/superio/winbond/w83627dhg/acpi/superio.asl
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@ -50,7 +50,7 @@ Device(SUPERIO_DEV) {
Field (CREG, ByteAcc, NoLock, Preserve) Field (CREG, ByteAcc, NoLock, Preserve)
{ {
PNP_ADDR_REG, 8, PNP_ADDR_REG, 8,
PNP_DATA_REG, 8 PNP_DATA_REG, 8
} }
IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
{ {
@ -118,14 +118,14 @@ Device(SUPERIO_DEV) {
Else { Return (0) } Else { Return (0) }
} }
/* PM: Switch to D0 by setting IPD low */ /* PM: Switch to D0 by setting IPD low */
Method (_PS0) { Method (_PS0) {
ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE)
Store (Zero, IPD) Store (Zero, IPD)
EXIT_CONFIG_MODE () EXIT_CONFIG_MODE ()
} }
/* PM: Switch to D3 by setting IPD high */ /* PM: Switch to D3 by setting IPD high */
Method (_PS3) { Method (_PS3) {
ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE)
Store (One, IPD) Store (One, IPD)
@ -133,7 +133,7 @@ Device(SUPERIO_DEV) {
} }
/* Suspend LED: Write given three-bit value into appropriate register. /* Suspend LED: Write given three-bit value into appropriate register.
From the datasheet: From the datasheet:
000 - drive pin constantly high 000 - drive pin constantly high
001 - drive 0.5Hz pulses 001 - drive 0.5Hz pulses
010 - drive pin constantly low 010 - drive pin constantly low

24
src/superio/winbond/w83627dhg/w83627dhg.h
View File

@ -6,20 +6,20 @@
#include <device/pnp_type.h> #include <device/pnp_type.h>
#define W83627DHG_FDC 0 /* Floppy */ #define W83627DHG_FDC 0 /* Floppy */
#define W83627DHG_PP 1 /* Parallel port */ #define W83627DHG_PP 1 /* Parallel port */
#define W83627DHG_SP1 2 /* Com1 */ #define W83627DHG_SP1 2 /* Com1 */
#define W83627DHG_SP2 3 /* Com2 */ #define W83627DHG_SP2 3 /* Com2 */
#define W83627DHG_KBC 5 /* PS/2 keyboard & mouse */ #define W83627DHG_KBC 5 /* PS/2 keyboard & mouse */
#define W83627DHG_SPI 6 /* Serial peripheral interface */ #define W83627DHG_SPI 6 /* Serial peripheral interface */
#define W83627DHG_WDTO_PLED 8 /* WDTO#, PLED */ #define W83627DHG_WDTO_PLED 8 /* WDTO#, PLED */
#define W83627DHG_ACPI 10 /* ACPI */ #define W83627DHG_ACPI 10 /* ACPI */
#define W83627DHG_HWM 11 /* Hardware monitor */ #define W83627DHG_HWM 11 /* Hardware monitor */
#define W83627DHG_PECI_SST 12 /* PECI, SST */ #define W83627DHG_PECI_SST 12 /* PECI, SST */
/* The following are handled using "virtual LDNs" (hence the _V suffix). */ /* The following are handled using "virtual LDNs" (hence the _V suffix). */
#define W83627DHG_GPIO6_V 7 /* GPIO6 */ #define W83627DHG_GPIO6_V 7 /* GPIO6 */
#define W83627DHG_GPIO2345_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5 */ #define W83627DHG_GPIO2345_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5 */
/* /*
* Virtual devices sharing the enables are encoded as follows: * Virtual devices sharing the enables are encoded as follows:

22
src/superio/winbond/w83627ehg/w83627ehg.h
View File

@ -4,19 +4,19 @@
#ifndef SUPERIO_WINBOND_W83627EHG_H #ifndef SUPERIO_WINBOND_W83627EHG_H
#define SUPERIO_WINBOND_W83627EHG_H #define SUPERIO_WINBOND_W83627EHG_H
#define W83627EHG_FDC 0 /* Floppy */ #define W83627EHG_FDC 0 /* Floppy */
#define W83627EHG_PP 1 /* Parallel port */ #define W83627EHG_PP 1 /* Parallel port */
#define W83627EHG_SP1 2 /* Com1 */ #define W83627EHG_SP1 2 /* Com1 */
#define W83627EHG_SP2 3 /* Com2 */ #define W83627EHG_SP2 3 /* Com2 */
#define W83627EHG_KBC 5 /* PS/2 keyboard & mouse */ #define W83627EHG_KBC 5 /* PS/2 keyboard & mouse */
#define W83627EHG_WDTO_PLED 8 /* Watchdog timer timeout, power LED */ #define W83627EHG_WDTO_PLED 8 /* Watchdog timer timeout, power LED */
#define W83627EHG_ACPI 10 /* ACPI */ #define W83627EHG_ACPI 10 /* ACPI */
#define W83627EHG_HWM 11 /* Hardware monitor */ #define W83627EHG_HWM 11 /* Hardware monitor */
/* The following are handled using "virtual LDNs" (hence the _V suffix). */ /* The following are handled using "virtual LDNs" (hence the _V suffix). */
#define W83627EHG_SFI_V 6 /* Serial flash interface (SFI) */ #define W83627EHG_SFI_V 6 /* Serial flash interface (SFI) */
#define W83627EHG_GPIO_GAME_MIDI_V 7 /* GPIO1, GPIO6, game port, MIDI */ #define W83627EHG_GPIO_GAME_MIDI_V 7 /* GPIO1, GPIO6, game port, MIDI */
#define W83627EHG_GPIO_SUSLED_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */ #define W83627EHG_GPIO_SUSLED_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */
/* /*
* Virtual devices sharing the enables are encoded as follows: * Virtual devices sharing the enables are encoded as follows:

160
src/superio/winbond/w83627hf/acpi/superio.asl
View File

@ -57,83 +57,83 @@ Device(SIO) {
OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
Field (CREG, ByteAcc, NoLock, Preserve) Field (CREG, ByteAcc, NoLock, Preserve)
{ {
PNP_ADDR_REG, 8, PNP_ADDR_REG, 8,
PNP_DATA_REG, 8 PNP_DATA_REG, 8
} }
IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
{ {
Offset (0x02), Offset (0x02),
RST, 1, /* Soft reset */ RST, 1, /* Soft reset */
, 7, , 7,
Offset (0x07), Offset (0x07),
LDN, 8, /* Logical device selector */ LDN, 8, /* Logical device selector */
Offset (0x20), Offset (0x20),
DID, 8, /* Device ID */ DID, 8, /* Device ID */
DREV, 8, /* Device Revision */ DREV, 8, /* Device Revision */
FDPW, 1, /* FDC Power Down */ FDPW, 1, /* FDC Power Down */
, 2, , 2,
PRPW, 1, /* PRT Power Down */ PRPW, 1, /* PRT Power Down */
UAPW, 1, /* UART A Power Down */ UAPW, 1, /* UART A Power Down */
UBPW, 1, /* UART B Power Down */ UBPW, 1, /* UART B Power Down */
HWPW, 1, /* HWM Power Down */ HWPW, 1, /* HWM Power Down */
, 1, , 1,
IPD, 1, /* Immediate Chip Power Down */ IPD, 1, /* Immediate Chip Power Down */
, 7, , 7,
PNPS, 1, /* PnP Address Select Register Default Value Mode */ PNPS, 1, /* PnP Address Select Register Default Value Mode */
, 1, , 1,
KBCR, 1, /* KBC enabled after system reset (read-only) */ KBCR, 1, /* KBC enabled after system reset (read-only) */
, 3, , 3,
CLKS, 1, /* Clock select */ CLKS, 1, /* Clock select */
AQ16, 1, /* 16bit Address Qualification */ AQ16, 1, /* 16bit Address Qualification */
FDCT, 1, /* Tristate FDC (?) */ FDCT, 1, /* Tristate FDC (?) */
, 2, , 2,
PRTT, 1, /* Tristate parallel port (?) */ PRTT, 1, /* Tristate parallel port (?) */
URAT, 1, /* Tristate UART A (?) */ URAT, 1, /* Tristate UART A (?) */
URBT, 1, /* Tristate UART B (?) */ URBT, 1, /* Tristate UART B (?) */
, 2, , 2,
URAI, 1, /* UART A Legacy IRQ Select Disable */ URAI, 1, /* UART A Legacy IRQ Select Disable */
URBI, 1, /* UART B Legacy IRQ Select Disable */ URBI, 1, /* UART B Legacy IRQ Select Disable */
PRTI, 1, /* Parallel Port Legacy IRQ/DRQ Select Disable */ PRTI, 1, /* Parallel Port Legacy IRQ/DRQ Select Disable */
FDCI, 1, /* FDC Legacy IRQ/DRQ Select Disable */ FDCI, 1, /* FDC Legacy IRQ/DRQ Select Disable */
, 1, , 1,
LCKC, 1, /* Lock Configuration Registers */ LCKC, 1, /* Lock Configuration Registers */
Offset (0x29), Offset (0x29),
IO3S, 8, /* GPIO3 pin selection register */ IO3S, 8, /* GPIO3 pin selection register */
Offset (0x30), Offset (0x30),
ACTR, 1, /* Logical device activation */ ACTR, 1, /* Logical device activation */
ACT1, 1, /* Logical part activation 1 (mostly unused) */ ACT1, 1, /* Logical part activation 1 (mostly unused) */
ACT2, 1, /* Logical part activation 2 (mostly unused) */ ACT2, 1, /* Logical part activation 2 (mostly unused) */
, 5, , 5,
Offset (0x60), Offset (0x60),
IO1H, 8, /* First I/O port base - high byte */ IO1H, 8, /* First I/O port base - high byte */
IO1L, 8, /* First I/O port base - low byte */ IO1L, 8, /* First I/O port base - low byte */
IO2H, 8, /* Second I/O port base - high byte */ IO2H, 8, /* Second I/O port base - high byte */
IO2L, 8, /* Second I/O port base - low byte */ IO2L, 8, /* Second I/O port base - low byte */
Offset (0x70), Offset (0x70),
IRQ0, 8, /* First IRQ */ IRQ0, 8, /* First IRQ */
Offset (0x72), Offset (0x72),
IRQ1, 8, /* First IRQ */ IRQ1, 8, /* First IRQ */
Offset (0x74), Offset (0x74),
DMA0, 8, /* DMA */ DMA0, 8, /* DMA */
Offset (0xE0), Offset (0xE0),
/* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */ /* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */
CRE0, 8, CRE0, 8,
CRE1, 8, CRE1, 8,
CRE2, 8, CRE2, 8,
CRE3, 8, CRE3, 8,
CRE4, 8, CRE4, 8,
Offset (0xF0), Offset (0xF0),
/* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */ /* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */
OPT1, 8, OPT1, 8,
OPT2, 8, OPT2, 8,
OPT3, 8, OPT3, 8,
OPT4, 8, OPT4, 8,
OPT5, 8, OPT5, 8,
OPT6, 8, OPT6, 8,
OPT7, 8, OPT7, 8,
OPT8, 8, OPT8, 8,
OPT9, 8, OPT9, 8,
OPTA, 8 OPTA, 8
} }
Method (_CRS) Method (_CRS)
@ -177,14 +177,14 @@ Device(SIO) {
Else { Return (0) } Else { Return (0) }
} }
/* PM: Switch to D0 by setting IPD low */ /* PM: Switch to D0 by setting IPD low */
Method (_PS0) { Method (_PS0) {
ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE)
Store (Zero, IPD) Store (Zero, IPD)
EXIT_CONFIG_MODE () EXIT_CONFIG_MODE ()
} }
/* PM: Switch to D3 by setting IPD high */ /* PM: Switch to D3 by setting IPD high */
Method (_PS3) { Method (_PS3) {
ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE)
Store (One, IPD) Store (One, IPD)
@ -315,23 +315,23 @@ Device(SIO) {
Field (FIO1, ByteAcc, NoLock, Preserve) Field (FIO1, ByteAcc, NoLock, Preserve)
{ {
Offset(0x02), Offset(0x02),
SELE, 2, SELE, 2,
RSTL, 1, RSTL, 1,
IDMA, 1, IDMA, 1,
ACT1, 1, ACT1, 1,
ACT2, 1, ACT2, 1,
ACT3, 1, ACT3, 1,
ACT4, 1, ACT4, 1,
Offset(0x04), Offset(0x04),
BSY1, 1, BSY1, 1,
BSY2, 1, BSY2, 1,
BSY3, 1, BSY3, 1,
BSY4, 1, BSY4, 1,
BUSY, 1, BUSY, 1,
NDMA, 1, NDMA, 1,
IODI, 1, IODI, 1,
RDY, 1, RDY, 1,
DATA, 8, DATA, 8,
} }
OperationRegion (FIO2, SystemIO, 0x3F7, 0x01) OperationRegion (FIO2, SystemIO, 0x3F7, 0x01)
Field (FIO2, ByteAcc, NoLock, Preserve) Field (FIO2, ByteAcc, NoLock, Preserve)
@ -567,7 +567,7 @@ Device(SIO) {
If (LEqual(IOAL, 4)) { If (LEqual(IOAL, 4)) {
Store(0x0, Local2) Store(0x0, Local2)
} else { } else {
Store(0x1, Local2) Store(0x1, Local2)
} }

18
src/superio/winbond/w83977tf/acpi/superio.asl
View File

@ -67,9 +67,9 @@ IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
OPT1, 8 OPT1, 8
} }
#define PNP_ENTER_MAGIC_1ST 0x87 #define PNP_ENTER_MAGIC_1ST 0x87
#define PNP_ENTER_MAGIC_2ND 0x87 #define PNP_ENTER_MAGIC_2ND 0x87
#define PNP_EXIT_MAGIC_1ST 0xaa #define PNP_EXIT_MAGIC_1ST 0xaa
#include <superio/acpi/pnp_config.asl> #include <superio/acpi/pnp_config.asl>
/* PM: indicate IPD (Immediate Power Down) bit state as D0/D3 */ /* PM: indicate IPD (Immediate Power Down) bit state as D0/D3 */
@ -84,13 +84,13 @@ Method (_PSC) {
#ifdef SUPERIO_SHOW_FDC #ifdef SUPERIO_SHOW_FDC
Device (FDC0) Device (FDC0)
{ {
Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID
Method (_STA, 0, NotSerialized) // _STA: Status Method (_STA, 0, NotSerialized) // _STA: Status
{ {
PNP_GENERIC_STA(W83977TF_FDC) PNP_GENERIC_STA(W83977TF_FDC)
} }
Method (_DIS, 0, NotSerialized) // _DIS: Disable Device Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
{ {
PNP_GENERIC_DIS(W83977TF_FDC) PNP_GENERIC_DIS(W83977TF_FDC)
} }
@ -300,7 +300,7 @@ Device (ECP)
Return (BUF6) Return (BUF6)
} }
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
{ {
StartDependentFn (0x01, 0x01) StartDependentFn (0x01, 0x01)
{ {
@ -326,7 +326,7 @@ Device (ECP)
EndDependentFn () EndDependentFn ()
}) })
Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
{ {
CreateByteField (Arg0, 0x02, IOLO) CreateByteField (Arg0, 0x02, IOLO)
CreateByteField (Arg0, 0x03, IOHI) CreateByteField (Arg0, 0x03, IOHI)
@ -366,5 +366,5 @@ Device (ECP)
*/ */
#define SUPERIO_KBC_LDN W83977TF_KBC #define SUPERIO_KBC_LDN W83977TF_KBC
#define SUPERIO_KBC_PS2M /* Mouse shares same LDN */ #define SUPERIO_KBC_PS2M /* Mouse shares same LDN */
#include <superio/acpi/pnp_kbc.asl> #include <superio/acpi/pnp_kbc.asl>