mb/google/brya: Add more gpios to lock
Add rest of soc sensitive gpios to lock for brya. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I41393e7a0e8bacb3cc98610f7101dabe66308f94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
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@ -80,7 +80,7 @@ static const struct pad_config gpio_table[] = {
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/* B13 : PLTRST# ==> PLT_RST_L */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14 : SPKR ==> GPP_B14_STRAP */
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PAD_NC(GPP_B14, NONE),
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PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG),
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/* B15 : TIME_SYNC0 ==> FP_USER_PRES_FP_L */
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PAD_CFG_GPI_LOCK(GPP_B15, NONE, LOCK_CONFIG),
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/* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */
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@ -118,7 +118,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE),
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/* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */
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PAD_NC(GPP_D0, NONE),
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PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
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/* D1 : ISH_GP1 ==> FP_RST_ODL */
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PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG),
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/* D2 : ISH_GP2 ==> EN_FP_PWR */
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@ -142,7 +142,7 @@ static const struct pad_config gpio_table[] = {
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/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
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PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG),
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/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
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PAD_NC(GPP_D12, NONE),
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PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
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/* D13 : ISH_UART0_RXD ==> CAM_PSW_L */
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PAD_CFG_GPI_INT_LOCK(GPP_D13, NONE, EDGE_BOTH, LOCK_CONFIG),
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/* D14 : ISH_UART0_TXD ==> SPKR_INT_L */
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@ -170,7 +170,7 @@ static const struct pad_config gpio_table[] = {
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/* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */
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PAD_CFG_GPO(GPP_E5, 1, DEEP),
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/* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */
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PAD_NC(GPP_E6, NONE),
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PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
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/* E7 : PROC_GP1 ==> EN_HPS_PWR */
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PAD_CFG_GPO(GPP_E7, 1, DEEP),
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/* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */
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@ -285,9 +285,9 @@ static const struct pad_config gpio_table[] = {
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */
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PAD_CFG_GPI(GPP_H12, NONE, DEEP),
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PAD_CFG_GPI_LOCK(GPP_H12, NONE, LOCK_CONFIG),
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/* H13 : I2C7_SCL ==> EN_PP3300_SD */
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PAD_NC(GPP_H13, UP_20K),
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PAD_NC_LOCK(GPP_H13, UP_20K, LOCK_CONFIG),
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/* H14 : NC */
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PAD_NC(GPP_H14, NONE),
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/* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
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