winbond/w83977tf: Add ACPI declarations
Add ACPI declarations to be incorporated into ACPI tables for mainboards with this super I/O. Change-Id: If113807901619bc0f4250607546be415f9e5e45b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Keith Hui
Martin Roth
parent
0b15b70b18
commit
e90e2e5e66
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de>
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* Copyright (C) 2013 secunet Security Networks AG
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* Copyright (C) 2017 Keith Hui <buurin@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Include this file into a southbridge ASL block and it will
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* expose the W83977TF/EF SuperIO and some of its functionality.
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*
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* Adapted from winbond/w83627dhg.
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*
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* It allows the change of IO ports, IRQs and DMA settings on logical
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* devices, disabling and reenabling logical devices and controlling power
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* saving mode on logical devices or the whole chip.
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*
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* Controllable through preprocessor defines:
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* SUPERIO_PNP_BASE I/O address of the first PnP configuration register
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* SUPERIO_SHOW_UARTA If defined, UARTA will be exposed.
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* SUPERIO_SHOW_UARTB If defined, UARTB will be exposed.
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* SUPERIO_SHOW_FDC If defined, floppy controller will be exposed.
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* SUPERIO_SHOW_LPT If defined, parallel port will be exposed.
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*/
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#define SUPERIO_CHIP_NAME W83977TF
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#include <superio/acpi/pnp.asl>
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#include <superio/winbond/w83977tf/w83977tf.h>
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/* Mutex for accesses to the configuration ports */
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Mutex(CRMX, 1)
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/* SuperIO configuration ports */
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OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
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Field (CREG, ByteAcc, NoLock, Preserve)
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{
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PNP_ADDR_REG, 8,
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PNP_DATA_REG, 8
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}
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IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
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{
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Offset (0x07),
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PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
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Offset (0x20),
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DID, 8, /* Device ID: TF=0x97, EF=0x52 */
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DREV, 8, /* Device revision */
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FDPW, 1,
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, 2,
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PRPW, 1,
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UAPW, 1, /* UART A Power Down */
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UBPW, 1, /* UART B Power Down */
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Offset (0x23),
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IPD, 1, /* Immediate Chip Power Down */
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Offset (0x30),
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PNP_DEVICE_ACTIVE, 8,
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Offset (0x60),
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PNP_IO0_HIGH_BYTE, 8,
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PNP_IO0_LOW_BYTE, 8,
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PNP_IO1_HIGH_BYTE, 8,
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PNP_IO1_LOW_BYTE, 8,
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PNP_IO2_HIGH_BYTE, 8,
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PNP_IO2_LOW_BYTE, 8,
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Offset (0x70),
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PNP_IRQ0, 8,
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Offset (0x72),
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PNP_IRQ1, 8,
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Offset (0x74),
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PNP_DMA0, 8,
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Offset (0xF0),
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OPT1, 8
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}
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#define PNP_ENTER_MAGIC_1ST 0x87
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#define PNP_ENTER_MAGIC_2ND 0x87
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#define PNP_EXIT_MAGIC_1ST 0xaa
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#include <superio/acpi/pnp_config.asl>
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/* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */
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Method (_PSC) {
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ENTER_CONFIG_MODE (0xFF)
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Store (IPD, Local0)
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EXIT_CONFIG_MODE ()
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If (Local0) { Return (2) }
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Else { Return (0) }
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}
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#ifdef SUPERIO_SHOW_FDC
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Device (FDC0)
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{
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Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID
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Method (_STA, 0, NotSerialized) // _STA: Status
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{
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PNP_GENERIC_STA(W83977TF_FDC)
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}
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Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
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{
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PNP_GENERIC_DIS(W83977TF_FDC)
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}
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Method (_CRS, 0)
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{
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Name (BUF0, ResourceTemplate ()
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{
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IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04, IO0)
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IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01, IO1)
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IRQ (Edge, ActiveHigh, Exclusive, Y08) {6}
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DMA (Compatibility, NotBusMaster, Transfer8, Y09) {2}
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})
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CreateWordField (BUF0, IO1._MIN, IO1I)
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CreateWordField (BUF0, IO1._MAX, IO1A)
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ENTER_CONFIG_MODE(W83977TF_FDC)
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/* OEM BIOS does not report actual programmed base port */
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/* xx0 is read from superio */
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PNP_READ_IO(PNP_IO0, BUF0, IO0)
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/* Store xx7 range first so the value isn't overwritten
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* for below */
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Add(IO0I, 7, IO1I)
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Store(IO1I, IO1A)
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/* Store xx2 range */
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Add(IO0I, 2, IO0I)
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Store(IO0I, IO0A)
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/* End OEM BIOS deficiency */
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PNP_READ_IRQ(PNP_IRQ0, BUF0, Y08)
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PNP_READ_DMA(PNP_DMA0, BUF0, Y09)
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EXIT_CONFIG_MODE()
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Return (BUF0)
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}
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04, )
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IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01, )
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IRQ (Edge, ActiveHigh, Exclusive, ) {6}
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DMA (Compatibility, NotBusMaster, Transfer8, ) {2}
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})
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Method (_SRS, 1, NotSerialized)
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{
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CreateByteField (Arg0, 0x02, IOLO)
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CreateByteField (Arg0, 0x03, IOHI)
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CreateWordField (Arg0, 0x11, IRQW)
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CreateByteField (Arg0, 0x15, DMAV)
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ENTER_CONFIG_MODE(W83977TF_FDC)
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/* FDC base port on 8-byte boundary. */
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And (IOLO, 0xF8, PNP_IO0_LOW_BYTE)
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Store (IOHI, PNP_IO0_HIGH_BYTE)
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Subtract (FindSetLeftBit (IRQW), 1, PNP_IRQ0)
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Subtract (FindSetLeftBit (DMAV), 1, PNP_DMA0)
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Store (One, PNP_DEVICE_ACTIVE)
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EXIT_CONFIG_MODE()
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}
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}
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#endif
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#ifdef SUPERIO_SHOW_LPT
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/* Standard LPT Parallel Port */
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Device (LPT)
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{
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Name (_HID, EisaId ("PNP0400"))
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Method (_STA, 0, NotSerialized)
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{
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ENTER_CONFIG_MODE(W83977TF_PP)
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And (OPT1, 0x02, Local0)
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If (LOr (IO0H, IO0L))
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{
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/* Report device not present if ECP is enabled */
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If (LEqual (Local0, 0x02))
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{
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EXIT_CONFIG_MODE()
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Return (0x00)
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}
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ElseIf (PNP_DEVICE_ACTIVE)
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{
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EXIT_CONFIG_MODE()
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Return (0x0F)
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}
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Else
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{
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EXIT_CONFIG_MODE()
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Return (0x0D)
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}
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}
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EXIT_CONFIG_MODE()
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Return (0)
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}
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Method (_DIS, 0, NotSerialized)
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{
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PNP_GENERIC_DIS(W83977TF_PP)
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF5, ResourceTemplate ()
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{
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IO (Decode16,0x0378,0x0378,0x00,0x04,Y0A)
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IRQ (Edge, ActiveHigh, Exclusive, Y0B)
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{7}
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})
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ENTER_CONFIG_MODE(W83977TF_PP)
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PNP_READ_IO(PNP_IO0,BUF5,Y0A)
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PNP_READ_IRQ(PNP_IRQ0,BUF5,Y0B)
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EXIT_CONFIG_MODE()
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Return (BUF5)
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}
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Name (_PRS, ResourceTemplate ()
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{
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StartDependentFn (0x01, 0x01)
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{
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IO (Decode16,0x0378,0x0378,0x00,0x08,)
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IRQ (Edge, ActiveHigh, Exclusive, )
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{5,7}
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}
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StartDependentFn (0x01, 0x01)
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{
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IO (Decode16,0x0278,0x0278,0x00,0x08,)
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IRQ (Edge, ActiveHigh, Exclusive, )
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{5,7}
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}
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StartDependentFn (0x01, 0x01)
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{
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IO (Decode16,0x03BC,0x03BC,0x00,0x04,)
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IRQ (Edge, ActiveHigh, Exclusive, )
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{5,7}
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}
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EndDependentFn ()
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})
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Method (_SRS, 1, NotSerialized)
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{
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CreateByteField (Arg0, 0x02, IOLO)
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CreateByteField (Arg0, 0x03, IOHI)
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CreateWordField (Arg0, 0x09, IRQW)
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ENTER_CONFIG_MODE(W83977TF_PP)
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Store (IOLO, PNP_IO0_LOW_BYTE)
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Store (IOHI, PNP_IO0_HIGH_BYTE)
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Subtract (FindSetLeftBit (IRQW), 1, PNP_IRQ0)
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Store (One, PNP_DEVICE_ACTIVE)
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EXIT_CONFIG_MODE()
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}
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}
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/* ECP Parallel Port */
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Device (ECP)
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{
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Name (_HID, EisaId ("PNP0401"))
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Method (_STA, 0, NotSerialized)
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{
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ENTER_CONFIG_MODE(W83977TF_PP)
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And (OPT1, 0x02, Local0)
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If (LOr (IO0H, IO0L))
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{
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If (LEqual (Local0, 0x02))
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{
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If (PNP_DEVICE_ACTIVE)
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{
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EXIT_CONFIG_MODE()
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Return (0x0F)
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}
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Else
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{
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EXIT_CONFIG_MODE()
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Return (0x05)
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}
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}
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}
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EXIT_CONFIG_MODE()
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Return (0x00)
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}
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Method (_DIS, 0, NotSerialized)
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{
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PNP_GENERIC_DIS(W83977TF_PP)
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF6, ResourceTemplate ()
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{
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IO (Decode16,0x0378,0x0378,0,4,IO0)
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IO (Decode16,0x0778,0x0778,0,4,IO1)
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IRQ (Edge, ActiveHigh, Exclusive, IR1) {7}
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DMA (Compatibility, NotBusMaster, Transfer8, Y0F) {1}
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})
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ENTER_CONFIG_MODE(W83977TF_PP)
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PNP_READ_IO(PNP_IO0, BUF6, IO0)
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PNP_READ_IO(PNP_IO0, BUF6, IO1)
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PNP_READ_IRQ(PNP_IRQ0, BUF6, IR1)
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PNP_READ_DMA(PNP_DMA0, BUF6, Y0F)
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/* Report a second port range that is 0x400 above base port. */
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CreateByteField (BUF6, 0x0B, I2HI)
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CreateByteField (BUF6, 0x0D, I2RH)
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Add (I2HI, 0x04, I2RH)
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Add (I2HI, 0x04, I2HI)
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EXIT_CONFIG_MODE()
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Return (BUF6)
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}
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Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
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{
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StartDependentFn (0x01, 0x01)
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{
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IO (Decode16,0x0378,0x0378,0,4,)
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IO (Decode16,0x0778,0x0778,0,4,)
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IRQ (Edge, ActiveHigh, Exclusive, ) {5,7}
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DMA (Compatibility, NotBusMaster, Transfer8, ) {0,1,3}
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}
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StartDependentFn (0x01, 0x01)
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{
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IO (Decode16,0x0278,0x0278,0,4,)
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IO (Decode16,0x0678,0x0678,0,4,)
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IRQ (Edge, ActiveHigh, Exclusive, ) {5,7}
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DMA (Compatibility, NotBusMaster, Transfer8, ) {0,1,3}
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}
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StartDependentFn (0x01, 0x01)
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{
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IO (Decode16,0x03BC,0x03BC,0,4,)
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IO (Decode16,0x07BC,0x07BC,0,4,)
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IRQ (Edge, ActiveHigh, Exclusive, ) {5,7}
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DMA (Compatibility, NotBusMaster, Transfer8, ) {0,1,3}
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}
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EndDependentFn ()
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})
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Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
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{
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CreateByteField (Arg0, 0x02, IOLO)
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CreateByteField (Arg0, 0x03, IOHI)
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CreateWordField (Arg0, 0x11, IRQW)
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CreateByteField (Arg0, 0x15, DMAC)
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ENTER_CONFIG_MODE(W83977TF_PP)
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Store (IOLO, PNP_IO0_LOW_BYTE)
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Store (IOHI, PNP_IO0_HIGH_BYTE)
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Subtract (FindSetLeftBit (IRQW), 1, PNP_IRQ0)
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Subtract (FindSetLeftBit (DMAC), 1, PNP_DMA0)
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Store (One, PNP_DEVICE_ACTIVE)
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EXIT_CONFIG_MODE()
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}
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}
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#endif
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#define SUPERIO_UART_PM_VAL 0
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#define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE
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#ifdef SUPERIO_SHOW_UARTA
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#define SUPERIO_UART_LDN W83977TF_SP1
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#define SUPERIO_UART_PM_REG UAPW
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef SUPERIO_SHOW_UARTB
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#define SUPERIO_UART_LDN W83977TF_SP2
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#define SUPERIO_UART_PM_REG UBPW
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#include <superio/acpi/pnp_uart.asl>
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#endif
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/*
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* TODO: IrDA device;
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* EF=LDN 3 aka UARTB
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* Some revisions of TF=LDN 6
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*/
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#define SUPERIO_KBC_LDN W83977TF_KBC
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#define SUPERIO_KBC_PS2M /* Mouse shares same LDN */
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#include <superio/acpi/pnp_kbc.asl>
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