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Cyan: Update DPTF parameters for higher temperature 

TEST=Run DPTF
CQ-DEPEND=CL:12729

Original-Reviewed-on: https://chromium-review.googlesource.com/295478
Original-Tested-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ifa58ad72105d377c00df577f0e16ff1148b70119
Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com>
Reviewed-on: https://review.coreboot.org/12747
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
T.H.Lin 2015-08-27 17:18:47 +08:00 committed by Martin Roth
parent 5942e065f8
commit e91e70cb92
2 changed files with 12 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
src/mainboard/google/cyan/acpi/dptf.asl
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@ -16,20 +16,18 @@
#define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_ID 0
#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
#define DPTF_TSR0_PASSIVE 48 #define DPTF_TSR0_PASSIVE 49
#define DPTF_TSR0_CRITICAL 70 #define DPTF_TSR0_CRITICAL 75
#define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
#define DPTF_TSR1_PASSIVE 60 #define DPTF_TSR1_PASSIVE 65
#define DPTF_TSR1_CRITICAL 70 #define DPTF_TSR1_CRITICAL 85
#define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_ID 2
#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
#define DPTF_TSR2_PASSIVE 55 #define DPTF_TSR2_PASSIVE 49
#define DPTF_TSR2_CRITICAL 70 #define DPTF_TSR2_CRITICAL 75
#define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_CHARGER
@ -50,18 +48,7 @@ Name (DTRT, Package () {
Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
/* CPU Effect on Temp Sensor 0 */ /* CPU Effect on Temp Sensor 0 */
Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },
#ifdef DPTF_ENABLE_CHARGER
/* Charger Effect on Temp Sensor 1 */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
#endif
/* CPU Effect on Temp Sensor 1 */
Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
/* CPU Effect on Temp Sensor 2 */
Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
}) })
Name (MPPC, Package () Name (MPPC, Package ()
@ -69,7 +56,7 @@ Name (MPPC, Package ()
0x2, /* Revision */ 0x2, /* Revision */
Package () { /* Power Limit 1 */ Package () { /* Power Limit 1 */
0, /* PowerLimitIndex, 0 for Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
1600, /* PowerLimitMinimum */ 2000, /* PowerLimitMinimum */
6200, /* PowerLimitMaximum */ 6200, /* PowerLimitMaximum */
1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMinimum */
1000, /* TimeWindowMaximum */ 1000, /* TimeWindowMaximum */

4
src/mainboard/google/cyan/onboard.h
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@ -78,3 +78,7 @@
#define BOARD_PRE_EVT 0x01 #define BOARD_PRE_EVT 0x01
#define BOARD_EVT 0x02 #define BOARD_EVT 0x02
#endif #endif
#define DPTF_CPU_PASSIVE 88
#define DPTF_CPU_CRITICAL 90