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mb/google/dedede/var/cappy2: Add Tpm2.0 device support 

Using Tpm2.0 device instead of the Cr50 in cappy2

BUG=b:191743435
BRANCH=dedede
TEST=tpm2.0 device function is ok

Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I216ceb6386ad57c9f1982187a4525d89869fa9c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56658
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sunwei Li 2021-07-28 20:17:46 +08:00 committed by Paul Fagerburg
parent 29924b24fa
commit e9211729a4
1 changed files with 5 additions and 8 deletions
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13
src/mainboard/google/dedede/variants/cappy2/overridetree.cb
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@ -4,10 +4,6 @@ chip soc/intel/jasperlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | Trackpad |
#| I2C1 | Digitizer |
#| I2C2 | Touchscreen |
@ -15,10 +11,6 @@ chip soc/intel/jasperlake
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
@ -87,6 +79,11 @@ chip soc/intel/jasperlake
device i2c 1a on end
end
end #I2C 4
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end # Discrete TPM
end # chip drivers/pc80/tpm
end # PCH eSPI
device pci 1f.3 on
chip drivers/generic/alc1015
register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"