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intel/sandybridge: add PCI IDs for 6-Series PCH 

The PCI ids are taken from:
	Intel® 6 Series Chipset and
	Intel® C200 Series Chipset
	Specification Update – NDA
	October 2013
	CDI / IBP#: 440377

Change-Id: Ib8418173fd36fd4109b3c4ec0d5543ca8e39ffa6
Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
Reviewed-on: http://review.coreboot.org/5226
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Chris Douglass 2014-02-14 13:51:52 -05:00 committed by Alexandru Gagniuc
parent 770c71f3ec
commit e92155fbe6
1 changed files with 26 additions and 1 deletions
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27
src/northbridge/intel/sandybridge/report_platform.c
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@ -59,11 +59,36 @@ static void report_cpu_info(void)
mode[aes], mode[txt], mode[vt]); mode[aes], mode[txt], mode[vt]);
} }
/* The PCI id name match comes from Intel document 472178 */
static struct { static struct {
u16 dev_id; u16 dev_id;
const char *dev_name; const char *dev_name;
} pch_table [] = { } pch_table [] = {
/* 6-series PCI ids from
* Intel® 6 Series Chipset and
* Intel® C200 Series Chipset
* Specification Update – NDA
* October 2013
* CDI / IBP#: 440377
*/
{0x1C41, "SFF Sample"},
{0x1C42, "Desktop Sample"},
{0x1C43, "Mobile Sample"},
{0x1C44, "Z68"},
{0x1C46, "P67"},
{0x1C47, "UM67"},
{0x1C49, "HM65"},
{0x1C4A, "H67"},
{0x1C4B, "HM67"},
{0x1C4C, "Q65"},
{0x1C4D, "QS67"},
{0x1C4E, "Q67"},
{0x1C4F, "QM67"},
{0x1C50, "B65"},
{0x1C52, "C202"},
{0x1C54, "C204"},
{0x1C56, "C206"},
{0x1C5C, "H61"},
/* 7-series PCI ids from Intel document 472178 */
{0x1E41, "Desktop Sample"}, {0x1E41, "Desktop Sample"},
{0x1E42, "Mobile Sample"}, {0x1E42, "Mobile Sample"},
{0x1E43, "SFF Sample"}, {0x1E43, "SFF Sample"},