mb/google/volteer/var/elemi: enable Genesys Logic GL9763E

Enable Genesys GL9763E as PCI-to-eMMC bridge.

BUG=b:171467336
BRANCH=volteer
TEST=emerge-volteer coreboot

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I858c12151df5b6fc19132869317edfa1b090335d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Wisley Chen 2020-10-31 01:24:43 +08:00 committed by Tim Wawrzynczak
parent bb1ada6d3a
commit e928391f74
2 changed files with 9 additions and 0 deletions

View File

@ -3,6 +3,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER
select BOARD_ROMSIZE_KB_32768
select DRIVERS_GENERIC_GPIO_KEYS
select DRIVERS_GENERIC_MAX98357A
select DRIVERS_GENESYSLOGIC_GL9763E
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_I2C_SX9310

View File

@ -6,6 +6,13 @@ chip soc/intel/tigerlake
register "IomTypeCPortPadCfg[0]" = "0x090E000A"
register "IomTypeCPortPadCfg[1]" = "0x090E000D"
# Enable EMMC PCIE 5 using clk 5
register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[5]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
@ -184,6 +191,7 @@ chip soc/intel/tigerlake
device generic 0 on end
end
end
device ref pcie_rp5 on end
device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.