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mainboard/winent: Remove unnecessary braces {} 

Fix coding style

Change-Id: I48a7bd4bd98d1a9d7b0ce4c12e09284fa4be6c7a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes HAOUAS 2018-01-31 23:18:14 +01:00 committed by Patrick Georgi
parent f46810171a
commit e93634caa0
4 changed files with 39 additions and 38 deletions
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5
src/mainboard/winent/mb6047/get_bus_conf.c
View File

@ -85,13 +85,12 @@ void get_bus_conf(void)
}
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0e, 0));
if (dev) {
if (dev)
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
else
printk(BIOS_DEBUG,
"ERROR - could not find PCI 1:%02x.0, using defaults\n",
sbdn + 0x0e);
}
/*I/O APICs: APIC ID Version State Address*/
apicid_base = get_apicid_base(1);

3
src/mainboard/winent/mb6047/irq_tables.c
View File

@ -141,9 +141,8 @@ unsigned long write_pirq_routing_table(unsigned long addr)
sum = pirq->checksum - sum;
if (sum != pirq->checksum) {
if (sum != pirq->checksum)
pirq->checksum = sum;
}
printk(BIOS_INFO, "done.\n");

3
src/mainboard/winent/mb6047/mainboard.c
View File

@ -36,9 +36,8 @@ static void mb6047_hwm_init(void)
printk(BIOS_INFO, "setting up hardware monitor at 0x%04x\n", (unsigned int)res->base);
/* Init hardware monitor. */
for (i = 0; i < ARRAY_SIZE(hwmtab); i++) {
for (i = 0; i < ARRAY_SIZE(hwmtab); i++)
hwm_write(res->base, hwmtab[i].bnk, hwmtab[i].idx, hwmtab[i].dat);
}
}
static void mb6047_mainboard_init(device_t dev)

66
src/mainboard/winent/mb6047/mptable.c
View File

@ -32,62 +32,66 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11,
res2mmio(res, 0, 0));
}
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x1, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res)
smp_write_ioapic(mc, apicid_ck804, 0x11,
res2mmio(res, 0, 0));
/* Initialize interrupt mapping*/
dword = 0x0120d218;
pci_write_config32(dev, 0x7c, dword);
dword = 0x0120d218;
pci_write_config32(dev, 0x7c, dword);
dword = 0x12008a00;
pci_write_config32(dev, 0x80, dword);
dword = 0x0000007d;
pci_write_config32(dev, 0x84, dword);
}
dword = 0x12008a00;
pci_write_config32(dev, 0x80, dword);
dword = 0x0000007d;
pci_write_config32(dev, 0x84, dword);
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
// Onboard ck804 smbus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_ck804_0, ((sbdn + 1) << 2) | 1, apicid_ck804, 0xa);
// Onboard ck804 USB 1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_ck804_0, ((sbdn + 2) << 2) | 0, apicid_ck804, 0x15);
// Onboard ck804 USB 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_ck804_0, ((sbdn + 2) << 2 ) | 1, apicid_ck804, 0x14);
// Onboard ck804 SATA 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_ck804_0, ((sbdn + 7) << 2 ) | 0, apicid_ck804, 0x17);
// Onboard ck804 SATA 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_ck804_0, ((sbdn + 8) << 2) | 0, apicid_ck804, 0x16);
//Slot PCIE x16
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00 << 2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
}
for (i = 0; i < 4; i++)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_ck804_5, (0x00 << 2) | i, apicid_ck804, 0x10 + (2 + i + 4 - sbdn%4)%4);
//Slot PCIE x4
for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00 << 2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
}
for (i = 0; i < 4; i++)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_ck804_4, (0x00 << 2) | i, apicid_ck804, 0x10 + (1 + i + 4 - sbdn%4)%4);
//Onboard SM720 VGA
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6 << 2)|0, apicid_ck804, 0x13); // 19
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_ck804_1, (6 << 2) | 0, apicid_ck804, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);