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amd/agesa/f14: Backport f15tn fixes from DDR3 in mtspd3.c 

Change-Id: I710efc3171e1653241f2dba1217a9560d2d99a16
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5802
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Edward O'Callaghan 2014-05-22 06:16:15 +10:00 committed by Kyösti Mälkki
parent cd30951e32
commit e93fe23440
1 changed files with 2 additions and 2 deletions
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4
src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c
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@ -290,7 +290,7 @@ MemTDIMMPresence3 (
// as a QR RDIMM with a rank Mux of x1 and therefore all four CS will be used. So an 8R LRDIMM will
// be marked as a QR even if Rank multiplication allows it to use only 2 logical ranks.
//
if (ChannelPtr->LrDimmPresent |= DimmMask) {
if ((ChannelPtr->LrDimmPresent & DimmMask) != 0) {
//
// LRDIMM Physical Ranks
//
@ -320,7 +320,7 @@ MemTDIMMPresence3 (
//
// Double Addr bus load value for dual rank DIMMs (Unless LRDIMM)
//
if ( ((ChannelPtr->LrDimmPresent |= DimmMask) == 0) && (Value8 == 2) ) {
if (((ChannelPtr->LrDimmPresent & DimmMask) == 0) && (Value8 == 2) ) {
Devwidth = Devwidth << 1;
}
//