amd/agesa/f14: Backport f15tn fixes from DDR3 in mtspd3.c
Change-Id: I710efc3171e1653241f2dba1217a9560d2d99a16 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5802 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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@ -290,7 +290,7 @@ MemTDIMMPresence3 (
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// as a QR RDIMM with a rank Mux of x1 and therefore all four CS will be used. So an 8R LRDIMM will
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// be marked as a QR even if Rank multiplication allows it to use only 2 logical ranks.
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//
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if (ChannelPtr->LrDimmPresent |= DimmMask) {
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if ((ChannelPtr->LrDimmPresent & DimmMask) != 0) {
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//
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// LRDIMM Physical Ranks
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//
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@ -320,7 +320,7 @@ MemTDIMMPresence3 (
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//
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// Double Addr bus load value for dual rank DIMMs (Unless LRDIMM)
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//
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if ( ((ChannelPtr->LrDimmPresent |= DimmMask) == 0) && (Value8 == 2) ) {
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if (((ChannelPtr->LrDimmPresent & DimmMask) == 0) && (Value8 == 2) ) {
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Devwidth = Devwidth << 1;
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}
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//
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