mb/google/brya/var/ghost: Delete variant
This project concluded and the coreboot implementation is no longer required. BUG=b:244596639 BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ie647dac7ad4879ec1b11baa0a8cb0990af56852f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67299 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jack Rosenthal
Martin L Roth
parent
d12e4f5088
commit
e95da5fdc0
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@ -60,17 +60,6 @@ config BOARD_GOOGLE_BASEBOARD_BRASK
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select SOC_INTEL_ALDERLAKE_PCH_P
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select TPM_GOOGLE_CR50
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config BOARD_GOOGLE_BASEBOARD_GHOST
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def_bool n
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select BOARD_GOOGLE_BASEBOARD_BRYA if BOARD_GOOGLE_GHOST4ADL
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select BOARD_GOOGLE_BASEBOARD_SKOLAS if !BOARD_GOOGLE_GHOST4ADL
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select DRIVERS_I2C_CS42L42
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select DRIVERS_I2C_MAX98396
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select DRIVERS_INTEL_MIPI_CAMERA
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select DRIVERS_NXP_UWB_SR1XX
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select GBB_FLAG_DISABLE_LID_SHUTDOWN if VBOOT
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select SOC_INTEL_COMMON_BLOCK_IPU
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config BOARD_GOOGLE_BASEBOARD_NISSA
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def_bool n
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select BOARD_GOOGLE_BRYA_COMMON
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@ -127,7 +116,6 @@ config DRIVER_TPM_I2C_BUS
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default 0x1 if BOARD_GOOGLE_BRASK
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default 0x1 if BOARD_GOOGLE_PRIMUS
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default 0x3 if BOARD_GOOGLE_PRIMUS4ES
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default 0x1 if BOARD_GOOGLE_BASEBOARD_GHOST
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default 0x1 if BOARD_GOOGLE_GIMBLE
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default 0x3 if BOARD_GOOGLE_GIMBLE4ES
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default 0x1 if BOARD_GOOGLE_REDRIX
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@ -193,9 +181,6 @@ config MAINBOARD_PART_NUMBER
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default "Brask" if BOARD_GOOGLE_BRASK
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default "Primus" if BOARD_GOOGLE_PRIMUS
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default "Primus4ES" if BOARD_GOOGLE_PRIMUS4ES
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default "Ghost" if BOARD_GOOGLE_GHOST
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default "Ghost4ADL" if BOARD_GOOGLE_GHOST4ADL
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default "Ghost4ES" if BOARD_GOOGLE_GHOST4ES
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default "Gimble" if BOARD_GOOGLE_GIMBLE
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default "Gimble4ES" if BOARD_GOOGLE_GIMBLE4ES
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default "Redrix" if BOARD_GOOGLE_REDRIX
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@ -234,7 +219,6 @@ config VARIANT_DIR
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default "brask" if BOARD_GOOGLE_BRASK
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default "primus" if BOARD_GOOGLE_PRIMUS
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default "primus4es" if BOARD_GOOGLE_PRIMUS4ES
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default "ghost" if BOARD_GOOGLE_BASEBOARD_GHOST
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default "gimble" if BOARD_GOOGLE_GIMBLE
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default "gimble4es" if BOARD_GOOGLE_GIMBLE4ES
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default "redrix" if BOARD_GOOGLE_REDRIX
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@ -57,19 +57,6 @@ config BOARD_GOOGLE_FELWINTER
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_GENESYSLOGIC_GL9755
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config BOARD_GOOGLE_GHOST
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bool "-> Ghost"
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select BOARD_GOOGLE_BASEBOARD_GHOST
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config BOARD_GOOGLE_GHOST4ADL
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bool "-> Ghost4ADL"
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select BOARD_GOOGLE_BASEBOARD_GHOST
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select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
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config BOARD_GOOGLE_GHOST4ES
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bool "-> Ghost4ES"
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select BOARD_GOOGLE_BASEBOARD_GHOST
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config BOARD_GOOGLE_GIMBLE
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bool "-> Gimble"
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select BOARD_GOOGLE_BASEBOARD_BRYA
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@ -1,6 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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romstage-y += memory.c
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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@ -1,423 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* This header block is used to supply information to arbitrage, a
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* google-internal tool. Updating it incorrectly will lead to issues,
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* so please don't update it unless a change is specifically required.
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* BaseID: EEF9BFAE6CA0D797
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* Overrides: 5e80bcfaea530ebe7e64b520ed0727daeb73a187
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*/
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* GPD0 : [NF1: BATLOW#] ==> BATLOW_L */
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PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
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/* GPD1 : [NF1: ACPRESENT] ==> ACPRESENT */
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PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
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/* GPD2 : [NF1: LAN_WAKE#] ==> EC_PCH_WAKE_ODL */
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PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
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/* GPD3 : [NF1: PWRBTN#] ==> EC_PCH_PWR_BTN_ODL */
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PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
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/* GPD4 : [NF1: SLP_S3#] ==> SLP_S3_R_L */
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PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
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/* GPD5 : [NF1: SLP_S4#] ==> SLP_S4_L */
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PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
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/* GPD6 : [NF1: SLP_A#] ==> SLP_A_L_CAP_SITE */
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PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
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/* GPD7 : GPD7_STRAP ==> Component NC */
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PAD_NC(GPD7, NONE),
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/* GPD8 : [NF1: SUSCLK] ==> PCH_SUSCLK */
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PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
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/* GPD9 : [NF1: SLP_WLAN#] ==> SLP_WLAN_L_CAP_SITE */
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PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
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/* GPD10 : [NF1: SLP_S5#] ==> SLP_S5_L */
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PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
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/* GPD11 : No heuristic was found useful */
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PAD_NC(GPD11, NONE),
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/* GPP_A0 : GPP_A0 ==> ESPI_PCH_D0_EC_R configured on reset, do not touch */
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/* GPP_A1 : GPP_A1 ==> ESPI_PCH_D1_EC_R configured on reset, do not touch */
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/* GPP_A2 : GPP_A2 ==> ESPI_PCH_D2_EC_R configured on reset, do not touch */
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/* GPP_A3 : GPP_A3 ==> ESPI_PCH_D3_EC_R configured on reset, do not touch */
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/* GPP_A4 : GPP_A4 ==> ESPI_PCH_CS_EC_R_L configured on reset, do not touch */
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/* GPP_A5 : GPP_A5 ==> ESPI_ALERT0 configured on reset, do not touch */
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/* GPP_A6 : GPP_A6 ==> ESPI_ALERT1 configured on reset, do not touch */
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/* GPP_A7 : PCH_UWB_WAKE */
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PAD_CFG_GPO(GPP_A7, 0, DEEP),
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/* GPP_A8 : HP_RST_ODL */
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PAD_CFG_GPO(GPP_A8, 1, PLTRST),
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/* GPP_A9 : GPP_A9 ==> ESPI_PCH_CLK_R configured on reset, do not touch */
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/* GPP_A10 : GPP_A10 ==> ESPI_PCH_RST_EC_L configured on reset, do not touch */
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/* GPP_A11 : [NF6: USB_C_GPP_A11] ==> EN_SPKR_PA */
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PAD_CFG_GPO(GPP_A11, 1, DEEP),
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/* GPP_A12 : EN_PP1800_UWB */
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PAD_CFG_GPO(GPP_A12, 0, DEEP),
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/* GPP_A13 : [NF6: USB_C_GPP_A13] ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* GPP_A14 : [NF1: USB_OC1# NF2: DDSP_HPD3 NF4: DISP_MISC3 NF6: USB_C_GPP_A14] ==> USB_C1_OC_ODL */
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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/* GPP_A15 : net NC is not present in the given design */
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PAD_NC(GPP_A15, NONE),
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/* GPP_A16 : net NC is not present in the given design */
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PAD_NC(GPP_A16, NONE),
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/* GPP_A17 : EN_PP16000H */
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PAD_CFG_GPO(GPP_A17, 1, DEEP),
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/* GPP_A18 : net NC is not present in the given design */
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PAD_NC(GPP_A18, NONE),
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/* GPP_A19 : No heuristic was found useful */
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PAD_NC(GPP_A19, NONE),
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/* GPP_A20 : net NC is not present in the given design */
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PAD_NC(GPP_A20, NONE),
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/* GPP_A21 : net NC is not present in the given design */
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PAD_NC(GPP_A21, NONE),
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/* GPP_A22 : net NC is not present in the given design */
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PAD_NC(GPP_A22, NONE),
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/* GPP_A23 : [NF1: ESPI_CS1# NF6: USB_C_GPP_A23] ==> AUD_HP_INT_L */
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PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH),
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/* GPP_B0 : [NF1: CORE_VID0 NF6: USB_C_GPP_B0] ==> SOC_VID0 */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* GPP_B1 : [NF1: CORE_VID1 NF6: USB_C_GPP_B1] ==> SOC_VID1 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* GPP_B2 : [NF1: VRALERT# NF6: USB_C_GPP_B2] ==> GPP_B2 */
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PAD_CFG_NF(GPP_B2, NONE, DEEP, NF6),
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/* GPP_B3 : MEM_CH_SEL */
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PAD_CFG_GPI(GPP_B3, NONE, DEEP),
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/* GPP_B4 : [NF1: PROC_GP3 NF4: ISH_GP5B NF6: USB_C_GPP_B4] ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 1, PLTRST),
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/* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> PCH_I2C_MISC_R_SDA */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
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/* GPP_B6 : [NF1: ISH_I2C0_SCL NF2: I2C2_SCL NF6: USB_C_GPP_B6] ==> PCH_I2C_MISC_R_SCL */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
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/* GPP_B7 : [NF1: ISH_I2C1_SDA NF2: I2C3_SDA NF6: USB_C_GPP_B7] ==> PCH_I2C_TCHSCR_R_SDA */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
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/* GPP_B8 : [NF1: ISH_I2C1_SCL NF2: I2C3_SCL NF6: USB_C_GPP_B8] ==> PCH_I2C_TCHSCR_R_SCL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
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/* GPP_B11 : [NF1: PMCALERT# NF6: USB_C_GPP_B11] ==> EN_PP3300_WLAN */
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PAD_CFG_GPO(GPP_B11, 1, DEEP),
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/* GPP_B12 : [NF1: SLP_S0# NF6: USB_C_GPP_B12] ==> SLP_S0_R_L */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* GPP_B13 : [NF1: PLTRST# NF6: USB_C_GPP_B13] ==> PLT_RST_L */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* GPP_B14 : GPP_B14_STRAP ==> Component NC */
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PAD_NC(GPP_B14, NONE),
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/* GPP_B15 : net NC is not present in the given design */
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PAD_NC(GPP_B15, NONE),
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/* GPP_B16 : [NF2: I2C5_SDA NF4: ISH_I2C2_SDA NF6: USB_C_GPP_B16] ==> PCH_I2C_TCHPAD_R_SDA */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
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/* GPP_B17 : [NF2: I2C5_SCL NF4: ISH_I2C2_SCL NF6: USB_C_GPP_B17] ==> PCH_I2C_TCHPAD_R_SCL */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
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/* GPP_B18 : GPP_B18_STRAP ==> Component NC */
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PAD_NC(GPP_B18, NONE),
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/* GPP_B23 : PCHHOT_ODL_STRAP ==> Component NC */
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PAD_NC(GPP_B23, NONE),
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/* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> EN_PP3300_TCHSCR */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* GPP_C1 : [NF1: SMBDATA NF6: USB_C_GPP_C1] ==> EN_TCHSCR */
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PAD_CFG_GPO(GPP_C1, 0, DEEP),
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/* GPP_C2 : GPP_C2_STRAP ==> Component NC */
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PAD_NC(GPP_C2, NONE),
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/* GPP_C3 : net NC is not present in the given design */
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PAD_NC(GPP_C3, NONE),
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/* GPP_C4 : [NF1: SML0DATA NF6: USB_C_GPP_C4] ==> EN_UCAM_PWR */
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PAD_CFG_GPO(GPP_C4, 0, DEEP),
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/* GPP_C5 : [NF1: SML0ALERT# NF6: USB_C_GPP_C5] ==> GPP_C5_BOOT_STRAP0 */
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PAD_CFG_NF(GPP_C5, NONE, DEEP, NF6),
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/* GPP_C6 : No heuristic was found useful */
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PAD_NC(GPP_C6, NONE),
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/* GPP_C7 : [NF1: SML1DATA NF6: USB_C_GPP_C7] ==> TCHSCR_INT */
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PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE),
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/* GPP_D0 : PCH_FP_BOOT0 ==> Component NC */
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PAD_NC(GPP_D0, NONE),
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/* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> FP_RST_ODL */
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PAD_CFG_GPO(GPP_D1, 1, DEEP),
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/* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* GPP_D3 : [NF1: ISH_GP3 NF2: BK3 NF5: SBK3 NF6: USB_C_GPP_D3] ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_D3, 1, DEEP),
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/* GPP_D4 : [NF1: IMGCLKOUT0 NF2: BK4 NF5: SBK4 NF6: USB_C_GPP_D4] ==> BT_DISABLE_L */
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PAD_CFG_GPO(GPP_D4, 1, DEEP),
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/* GPP_D5 : net NC is not present in the given design */
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PAD_NC(GPP_D5, NONE),
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/* GPP_D6 : [NF1: SRCCLKREQ1# NF6: USB_C_GPP_D6] ==> SSD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
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/* GPP_D7 : net NC is not present in the given design */
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PAD_NC(GPP_D7, NONE),
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/* GPP_D8 : net NC is not present in the given design */
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PAD_NC(GPP_D8, NONE),
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/* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> USB_C0_LSX_TX */
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PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4),
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/* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> USB_C0_LSX_RX_STRAP */
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PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4),
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/* GPP_D11 : net NC is not present in the given design */
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PAD_NC(GPP_D11, NONE),
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/* GPP_D12 : GPP_D12_STRAP ==> Component NC */
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PAD_NC(GPP_D12, NONE),
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/* GPP_D13 : No heuristic was found useful */
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PAD_NC(GPP_D13, NONE),
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/* GPP_D14 : No heuristic was found useful */
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PAD_NC(GPP_D14, NONE),
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/* GPP_D15 : net NC is not present in the given design */
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PAD_NC(GPP_D15, NONE),
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/* GPP_D16 : net NC is not present in the given design */
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PAD_NC(GPP_D16, NONE),
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/* GPP_D17 : net NC is not present in the given design */
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PAD_NC(GPP_D17, NONE),
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/* GPP_D18 : net NC is not present in the given design */
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PAD_NC(GPP_D18, NONE),
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/* GPP_D19 : No heuristic was found useful */
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PAD_NC(GPP_D19, NONE),
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/* GPP_E0 : net NC is not present in the given design */
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PAD_NC(GPP_E0, NONE),
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/* GPP_E1 : MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_E1, NONE, DEEP),
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/* GPP_E2 : MEM_STRAP_1 */
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PAD_CFG_GPI(GPP_E2, NONE, DEEP),
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/* GPP_E3 : MEM_STRAP_0 */
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PAD_CFG_GPI(GPP_E3, NONE, DEEP),
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/* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> USB4_BB_RT_FORCE_PWR */
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PAD_CFG_GPO(GPP_E4, 1, DEEP),
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/* GPP_E5 : net NC is not present in the given design */
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PAD_NC(GPP_E5, NONE),
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/* GPP_E6 : GPP_E6_STRAP ==> Component NC */
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PAD_NC(GPP_E6, NONE),
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/* GPP_E7 : MEM_STRAP_3 */
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PAD_CFG_GPI(GPP_E7, NONE, DEEP),
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/* GPP_E8 : [NF6: USB_C_GPP_E8] ==> WIFI_DISABLE_L */
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PAD_CFG_GPO(GPP_E8, 1, DEEP),
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/* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> USB_C0_OC_ODL */
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* GPP_E10 : [NF2: THC0_SPI1_CS# NF6: USB_C_GPP_E10 NF7: GSPI0_CS0#] ==> PCH_GSPI0_CS_L_UWB */
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7),
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/* GPP_E11 : [NF2: THC0_SPI1_CLK NF6: USB_C_GPP_E11 NF7: GSPI0_CLK] ==> PCH_GSPI0_CLK_UWB_R */
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PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7),
|
||||
/* GPP_E12 : [NF2: THC0_SPI1_IO1 NF5: I2C0A_SDA NF6: USB_C_GPP_E12 NF7: GSPI0_MISO] ==> PCH_GSPI0_DI_UWB_DO */
|
||||
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7),
|
||||
/* GPP_E13 : [NF2: THC0_SPI1_IO0 NF5: I2C0A_SCL NF6: USB_C_GPP_E13 NF7: GSPI0_MOSI] ==> PCH_GSPI0_DO_UWB_DI_R */
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7),
|
||||
/* GPP_E14 : [NF1: DDSP_HPDA NF2: DISP_MISCA NF6: USB_C_GPP_E14] ==> SOC_EDP_HPD */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
/* GPP_E15 : RSVD_TP ==> PCH_WP_OD */
|
||||
PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG),
|
||||
/* GPP_E16 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_E16, NONE),
|
||||
/* GPP_E17 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
/* GPP_E18 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_E18, NONE),
|
||||
/* GPP_E19 : GPP_E19_STRAP ==> Component NC */
|
||||
PAD_NC(GPP_E19, NONE),
|
||||
/* GPP_E20 : [NF1: DDP2_CTRLCLK NF4: TBT_LSX1_TXD NF5: BSSB_LS1_RX NF6: USB_C_GPP_E20] ==> USB_C1_LSX_TX */
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
|
||||
/* GPP_E21 : [NF1: DDP2_CTRLDATA NF4: TBT_LSX1_RXD NF5: BSSB_LS1_TX NF6: USB_C_GPP_E21] ==> USB_C1_LSX_RX_STRAP */
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
|
||||
/* GPP_E22 : DNX_STRAP ==> Component NC */
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
/* GPP_E23 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
/* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
/* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
/* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
/* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
/* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
/* GPP_F5 : [NF2: MODEM_CLKREQ NF3: CRF_XTAL_CLKREQ NF6: USB_C_GPP_F5] ==> CNV_CLKREQ0 */
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
|
||||
/* GPP_F6 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
/* GPP_F7 : GPP_F7_STRAP ==> Component NC */
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
/* GPP_F9 : [] ==> SLP_S0_GATE_R */
|
||||
PAD_CFG_GPO(GPP_F9, 1, DEEP),
|
||||
/* GPP_F10 : GPP_F10_STRAP ==> Component NC */
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
/* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK NF6: USB_C_GPP_F11] ==> GSPI_PCH_CLK_FPMCU_R */
|
||||
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
|
||||
/* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL NF6: USB_C_GPP_F12] ==> GSPI_PCH_DO_FPMCU_DI_R */
|
||||
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
|
||||
/* GPP_F13 : [NF1: GSXSLOAD NF3: THC1_SPI2_IO1 NF4: GSPI1_MISO NF5: I2C1A_SDA NF6: USB_C_GPP_F13] ==> GSPI_PCH_DI_FPMCU_DO */
|
||||
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
|
||||
/* GPP_F14 : [NF1: GSXDIN NF3: THC1_SPI2_IO2 NF6: USB_C_GPP_F14] ==> TCHPAD_INT_L */
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* GPP_F15 : [NF1: GSXSRESET# NF3: THC1_SPI2_IO3 NF6: USB_C_GPP_F15] ==> FPMCU_PCH_INT_L */
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI_CS0# NF6: USB_C_GPP_F16] ==> GSPI_PCH_CS_FPMCU_R_L */
|
||||
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
|
||||
/* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> EC_PCH_INT_ODL */
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
/* GPP_F19 : [NF1: SRCCLKREQ6# NF6: USB_C_GPP_F19] ==> GPP_F19 */
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF6),
|
||||
/* GPP_F20 : [] ==> UCAM_RST_L */
|
||||
PAD_CFG_GPO(GPP_F20, 0, DEEP),
|
||||
/* GPP_F21 : UWB_PCH_INT */
|
||||
PAD_CFG_GPI_INT(GPP_F21, NONE, PLTRST, LEVEL),
|
||||
/* GPP_F22 : No heuristic was found useful */
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
/* GPP_F23 : No heuristic was found useful */
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
/* GPP_H0 : [NF6: USB_C_GPP_H0] ==> GPP_H0_BOOT_STRAP1 */
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF6),
|
||||
/* GPP_H1 : [NF6: USB_C_GPP_H1] ==> GPP_H1_BOOT_STRAP2 */
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF6),
|
||||
/* GPP_H2 : [NF6: USB_C_GPP_H2] ==> GPP_H2_BOOT_STRAP3 */
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF6),
|
||||
/* GPP_H3 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_H3, NONE),
|
||||
/* GPP_H4 : [NF1: I2C0_SDA NF6: USB_C_GPP_H4] ==> PCH_I2C_AUD_R_SDA */
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
/* GPP_H5 : [NF1: I2C0_SCL NF6: USB_C_GPP_H5] ==> PCH_I2C_AUD_R_SCL */
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
/* GPP_H6 : [NF1: I2C1_SDA NF6: USB_C_GPP_H6] ==> PCH_I2C_TPM_R_SDA */
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
/* GPP_H7 : [NF1: I2C1_SCL NF6: USB_C_GPP_H7] ==> PCH_I2C_TPM_R_SCL */
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
/* GPP_H8 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_H8, NONE),
|
||||
/* GPP_H9 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_H9, NONE),
|
||||
/* GPP_H10 : [NF2: UART0_RXD NF3: M2_SKT2_CFG0 NF6: USB_C_GPP_H10] ==> UART_PCH_RX_DBG_TX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* GPP_H11 : [NF2: UART0_TXD NF3: M2_SKT2_CFG1 NF6: USB_C_GPP_H11] ==> UART_PCH_TX_DBG_RX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
/* GPP_H12 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
/* GPP_H13 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
/* GPP_H15 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
/* GPP_H17 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_H17, NONE),
|
||||
/* GPP_H18 : [NF1: PROC_C10_GATE# NF6: USB_C_GPP_H18] ==> CPU_C10_GATE_L */
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
/* GPP_H19 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
/* GPP_H20 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
/* GPP_H21 : [NF1: IMGCLKOUT2 NF6: USB_C_GPP_H21] ==> UCAM_MCLK_R */
|
||||
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
|
||||
/* GPP_H22 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
/* GPP_H23 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
/* GPP_R0 : [NF1: HDA_BCLK NF2: I2S0_SCLK NF3: DMIC_CLK_B0 NF4: HDAPROC_BCLK] ==> I2S_HP_SCLK_R */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
|
||||
/* GPP_R1 : [NF1: HDA_SYNC NF2: I2S0_SFRM NF3: DMIC_CLK_B1] ==> I2S_HP_SFRM_R */
|
||||
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
|
||||
/* GPP_R2 : [NF1: HDA_SDO NF2: I2S0_TXD NF4: HDAPROC_SDO] ==> I2S_PCH_TX_HP_RX_STRAP */
|
||||
PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
|
||||
/* GPP_R3 : [NF1: HDA_SDI0 NF2: I2S0_RXD NF4: HDAPROC_SDI] ==> I2S_PCH_RX_HP_TX */
|
||||
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
|
||||
/* GPP_R4 : [NF1: HDA_RST# NF2: I2S2_SCLK NF3: DMIC_CLK_A0] ==> DMIC_CLK0_R */
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
|
||||
/* GPP_R5 : [NF1: HDA_SDI1 NF2: I2S2_SFRM NF3: DMIC_DATA0] ==> DMIC_DATA0_R */
|
||||
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
|
||||
/* GPP_R6 : [NF2: I2S2_TXD NF3: DMIC_CLK_A1] ==> DMIC_CLK1_R */
|
||||
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
|
||||
/* GPP_R7 : [NF2: I2S2_RXD NF3: DMIC_DATA1] ==> DMIC_DATA1_R */
|
||||
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
|
||||
/* GPP_S0 : [NF1: SNDW0_CLK NF4: I2S1_SCLK] ==> I2S_SPKR_SCLK_R */
|
||||
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
|
||||
/* GPP_S1 : [NF1: SNDW0_DATA NF4: I2S1_SFRM] ==> I2S_SPKR_SFRM_R */
|
||||
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
|
||||
/* GPP_S2 : [NF1: SNDW1_CLK NF2: DMIC_CKLA0 NF4: I2S1_TXD] ==> I2S_PCH_TX_SPKR_RX_R */
|
||||
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
|
||||
/* GPP_S3 : [NF1: SNDW1_DATA NF2: DMIC_DATA0 NF4: I2S1_RXD] ==> I2S_PCH_RX_SPKR_TX */
|
||||
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
|
||||
/* GPP_S4 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
/* GPP_S5 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
/* GPP_S6 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
/* GPP_S7 : net NC is not present in the given design */
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
/* GPP_T2 : No heuristic was found useful */
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
/* GPP_T3 : No heuristic was found useful */
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* B4 : PROC_GP3 ==> SSD_PERST_L */
|
||||
PAD_CFG_GPO(GPP_B4, 0, DEEP),
|
||||
/*
|
||||
* D1 : ISH_GP1 ==> FP_RST_ODL
|
||||
* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
|
||||
* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
|
||||
* early on in bootblock, followed by enabling of power. Reset signal is deasserted
|
||||
* later on in ramstage. Since reset signal is asserted in bootblock, it results in
|
||||
* FPMCU not working after a S3 resume. This is a known issue.
|
||||
*/
|
||||
PAD_CFG_GPO(GPP_D1, 0, DEEP),
|
||||
/* D2 : ISH_GP2 ==> EN_FP_PWR */
|
||||
PAD_CFG_GPO(GPP_D2, 1, DEEP),
|
||||
/* GPP_D3 : [NF1: ISH_GP3 NF2: BK3 NF5: SBK3 NF6: USB_C_GPP_D3] ==> EN_PP3300_SSD */
|
||||
PAD_CFG_GPO(GPP_D3, 1, DEEP),
|
||||
/* E15 : RSVD_TP ==> PCH_WP_OD */
|
||||
PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG),
|
||||
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
|
||||
/* TPM is on I2C port 1 */
|
||||
/* H6 : [NF1: I2C1_SDA NF6: USB_C_GPP_H6] ==> PCH_I2C_TPM_R_SDA */
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
/* H7 : [NF1: I2C1_SCL NF6: USB_C_GPP_H7] ==> PCH_I2C_TPM_R_SCL */
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
|
||||
/* Mem straps */
|
||||
/* B3 : PROC_GP2 ==> MEM_CH_SEL */
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
/* E3 : PROC_GP0 ==> MEM_STRAP_0 */
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
/* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
/* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */
|
||||
PAD_CFG_GPI(GPP_E1, NONE, DEEP),
|
||||
/* E7 : PROC_GP1 ==> MEM_STRAP_3 */
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
};
|
||||
|
||||
static const struct pad_config romstage_gpio_table[] = {
|
||||
/* B4 : PROC_GP3 ==> SSD_PERST_L */
|
||||
PAD_CFG_GPO(GPP_B4, 1, DEEP),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_gpio_override_table(size_t *num)
|
||||
{
|
||||
*num = 0;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_romstage_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(romstage_gpio_table);
|
||||
return romstage_gpio_table;
|
||||
}
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __VARIANT_EC_H__
|
||||
#define __VARIANT_EC_H__
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
#endif
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#endif
|
||||
|
|
@ -1,118 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct mb_cfg baseboard_memcfg = {
|
||||
.type = MEM_TYPE_LP5X,
|
||||
|
||||
/*
|
||||
* DQ byte map
|
||||
*
|
||||
* To calculate from schematics, reference
|
||||
* ADL_LP5_DqMapCpu2Dram sheet of this spreadsheet:
|
||||
* https://cdrdv2.intel.com/v1/dl/getContent/573387
|
||||
*/
|
||||
.lpx_dq_map = {
|
||||
.ddr0 = {
|
||||
.dq0 = { 5, 0, 4, 1, 2, 6, 7, 3 },
|
||||
.dq1 = { 11, 15, 13, 12, 10, 14, 8, 9 },
|
||||
},
|
||||
.ddr1 = {
|
||||
.dq0 = { 9, 10, 11, 8, 13, 14, 12, 15 },
|
||||
.dq1 = { 0, 2, 1, 3, 7, 5, 6, 4 },
|
||||
},
|
||||
.ddr2 = {
|
||||
.dq0 = { 3, 7, 2, 6, 4, 1, 5, 0 },
|
||||
.dq1 = { 12, 14, 15, 13, 11, 10, 8, 9 },
|
||||
},
|
||||
.ddr3 = {
|
||||
.dq0 = { 15, 14, 12, 13, 10, 9, 11, 8 },
|
||||
.dq1 = { 7, 6, 4, 5, 0, 3, 1, 2 },
|
||||
},
|
||||
.ddr4 = {
|
||||
.dq0 = { 15, 14, 12, 13, 10, 9, 8, 11 },
|
||||
.dq1 = { 1, 3, 0, 2, 5, 6, 7, 4 },
|
||||
},
|
||||
.ddr5 = {
|
||||
.dq0 = { 9, 10, 11, 8, 12, 15, 13, 14 },
|
||||
.dq1 = { 3, 7, 2, 6, 0, 4, 5, 1 },
|
||||
},
|
||||
.ddr6 = {
|
||||
.dq0 = { 11, 8, 10, 9, 12, 14, 13, 15 },
|
||||
.dq1 = { 0, 7, 1, 2, 6, 4, 3, 5 },
|
||||
},
|
||||
.ddr7 = {
|
||||
.dq0 = { 1, 2, 3, 0, 7, 5, 6, 4 },
|
||||
.dq1 = { 15, 14, 11, 13, 8, 9, 12, 10 },
|
||||
},
|
||||
},
|
||||
|
||||
/*
|
||||
* DQS CPU<>DRAM map
|
||||
*
|
||||
* To calculate from schematics, reference
|
||||
* MTL_RPL_ADL_LP5_DqsMapCpu2Dram sheet of this spreadsheet:
|
||||
* https://cdrdv2.intel.com/v1/dl/getContent/573387
|
||||
*/
|
||||
.lpx_dqs_map = {
|
||||
.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
},
|
||||
|
||||
/* Enable Early Command Training */
|
||||
.ect = true,
|
||||
|
||||
.UserBd = BOARD_TYPE_MOBILE,
|
||||
|
||||
.lp5x_config = {
|
||||
/*
|
||||
* CA and CS signals are in descending order.
|
||||
*
|
||||
* Reference the MTL_RPL_ADL_LP5_CccConfig sheet of
|
||||
* this spreadsheet for instructions:
|
||||
* https://cdrdv2.intel.com/v1/dl/getContent/573387
|
||||
*/
|
||||
.ccc_config = 0xff,
|
||||
},
|
||||
};
|
||||
|
||||
const struct mb_cfg *variant_memory_params(void)
|
||||
{
|
||||
return &baseboard_memcfg;
|
||||
}
|
||||
|
||||
int variant_memory_sku(void)
|
||||
{
|
||||
/*
|
||||
* Memory configuration board straps
|
||||
* - MEM_STRAP_0: GPP_E3
|
||||
* - MEM_STRAP_1: GPP_E2
|
||||
* - MEM_STRAP_2: GPP_E1
|
||||
* - MEM_STRAP_3: GPP_E7
|
||||
*
|
||||
* MEM_STRAP_0 is LSB, and MEM_STRAP_3 is MSB.
|
||||
*/
|
||||
gpio_t spd_gpios[] = {
|
||||
GPP_E3,
|
||||
GPP_E2,
|
||||
GPP_E1,
|
||||
GPP_E7,
|
||||
};
|
||||
|
||||
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
|
||||
}
|
||||
|
||||
bool variant_is_half_populated(void)
|
||||
{
|
||||
/* GPIO_MEM_CH_SEL is GPP_B3 */
|
||||
return gpio_get(GPP_B3);
|
||||
}
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/ghost/memory src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt
|
||||
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9JCNNNBK3MLYR-N6E, MT62F512M32D2DR-031 WT:B
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 1(0b0001) Parts = H58G56AK6BX069
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-5.hex # ID = 2(0b0010) Parts = K3LKLKL0EM-MGCN
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = MT62F1G32D2DS-026 WT:B
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/ghost/memory src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt
|
||||
|
||||
DRAM Part Name ID to assign
|
||||
H9JCNNNBK3MLYR-N6E 0 (0000)
|
||||
H58G56AK6BX069 1 (0001)
|
||||
MT62F512M32D2DR-031 WT:B 0 (0000)
|
||||
K3LKLKL0EM-MGCN 2 (0010)
|
||||
MT62F1G32D2DS-026 WT:B 3 (0011)
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
# This is a CSV file containing a list of memory parts used by this variant.
|
||||
# One part per line with an optional fixed ID in column 2.
|
||||
# Only include a fixed ID if it is required for legacy reasons!
|
||||
# Generated IDs are dependent on the order of parts in this file,
|
||||
# so new parts must always be added at the end of the file!
|
||||
#
|
||||
# Generate an updated Makefile.inc and dram_id.generated.txt by running the
|
||||
# part_id_gen tool from util/spd_tools.
|
||||
# See util/spd_tools/README.md for more details and instructions.
|
||||
|
||||
# Part Name
|
||||
H9JCNNNBK3MLYR-N6E
|
||||
H58G56AK6BX069
|
||||
MT62F512M32D2DR-031 WT:B
|
||||
K3LKLKL0EM-MGCN
|
||||
MT62F1G32D2DS-026 WT:B
|
||||
|
|
@ -1,294 +0,0 @@
|
|||
chip soc/intel/alderlake
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| GSPI1 | FPMCU |
|
||||
#| I2C0 | Audio |
|
||||
#| I2C1 | cr50 TPM. Early init is |
|
||||
#| | required to set up a BAR |
|
||||
#| | for TPM communication |
|
||||
#| I2C2 | Misc (Cam, Display, LED) |
|
||||
#| I2C3 | Touchscreen |
|
||||
#| I2C4 | NC |
|
||||
#| I2C5 | Touchpad |
|
||||
#+-------------------+---------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[1] = {
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[2] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[3] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[5] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
}"
|
||||
|
||||
# I2C Port Config
|
||||
register "serial_io_i2c_mode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
# GSPI config
|
||||
register "serial_io_gspi_mode" = "{
|
||||
[PchSerialIoIndexGSPI0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexGSPI1] = PchSerialIoPci,
|
||||
}"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1
|
||||
register "usb2_ports[2]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[3]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # DCI port
|
||||
register "usb2_ports[5]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_EMPTY"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # DCI port
|
||||
register "usb3_ports[3]" = "USB3_PORT_EMPTY"
|
||||
|
||||
register "tcss_ports[0]" = "TCSS_PORT_EMPTY"
|
||||
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" # TypeC C1
|
||||
register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" # TypeC C0
|
||||
|
||||
device domain 0 on
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp6 off end
|
||||
device ref pcie_rp7 off end
|
||||
device ref pcie_rp8 off end
|
||||
device ref tcss_dma0 on
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
|
||||
use tcss_usb3_port2 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref tcss_dma1 on
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
|
||||
use tcss_usb3_port3 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c0 on
|
||||
chip drivers/i2c/cs42l42
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
|
||||
register "ts_inv" = "true"
|
||||
register "ts_dbnc_rise" = "RISE_DEB_1000_MS"
|
||||
register "ts_dbnc_fall" = "FALL_DEB_0_MS"
|
||||
register "btn_det_init_dbnce" = "100"
|
||||
register "btn_det_event_dbnce" = "10"
|
||||
register "bias_lvls[0]" = "15"
|
||||
register "bias_lvls[1]" = "8"
|
||||
register "bias_lvls[2]" = "4"
|
||||
register "bias_lvls[3]" = "1"
|
||||
register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW"
|
||||
register "hs_bias_sense_disable" = "true"
|
||||
device i2c 48 on end
|
||||
end
|
||||
chip drivers/i2c/max98396
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
|
||||
register "vmon_slot_no" = "0"
|
||||
register "imon_slot_no" = "1"
|
||||
register "uid" = "0"
|
||||
register "desc" = ""Right Speaker Amp""
|
||||
register "name" = ""MAXR""
|
||||
device i2c 3c on end
|
||||
end
|
||||
chip drivers/i2c/max98396
|
||||
register "vmon_slot_no" = "2"
|
||||
register "imon_slot_no" = "3"
|
||||
register "uid" = "1"
|
||||
register "desc" = ""Left Speaker Amp""
|
||||
register "name" = ""MAXL""
|
||||
device i2c 3d on end
|
||||
end
|
||||
end
|
||||
device ref i2c1 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end
|
||||
device ref i2c2 on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = ""OVTI5675""
|
||||
register "acpi_uid" = "0"
|
||||
register "acpi_name" = ""CAM0""
|
||||
register "chip_name" = ""Ov 5675 Camera""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
|
||||
|
||||
register "ssdb.lanes_used" = "2"
|
||||
register "ssdb.link_used" = "1"
|
||||
register "num_freq_entries" = "1"
|
||||
register "link_freq[0]" = "DEFAULT_LINK_FREQ"
|
||||
register "remote_name" = ""IPU0""
|
||||
register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
|
||||
|
||||
register "has_power_resource" = "1"
|
||||
|
||||
# Controls
|
||||
register "clk_panel.clks[0].clknum" = "IMGCLKOUT_2"
|
||||
register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
|
||||
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_C4" # EN_UCAM_PWR
|
||||
register "gpio_panel.gpio[1].gpio_num" = "GPP_F20" # UCAM_RST_L
|
||||
|
||||
# ON
|
||||
register "on_seq.ops_cnt" = "4"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
|
||||
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
|
||||
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)"
|
||||
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
|
||||
|
||||
# OFF
|
||||
register "off_seq.ops_cnt" = "3"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
|
||||
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 36 on end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
register "acpi_uid" = "1"
|
||||
register "acpi_name" = ""NVM0""
|
||||
register "chip_name" = ""M24C64X""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_NVM"
|
||||
register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
|
||||
|
||||
register "nvm_size" = "0x2000"
|
||||
register "nvm_pagesize" = "1"
|
||||
register "nvm_readonly" = "1"
|
||||
register "nvm_width" = "0x10"
|
||||
register "nvm_compat" = ""atmel,24c64""
|
||||
device i2c 50 on end
|
||||
end
|
||||
end
|
||||
device ref ipu on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "0x50000"
|
||||
register "acpi_name" = ""IPU0""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
|
||||
|
||||
register "cio2_num_ports" = "1"
|
||||
register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used
|
||||
register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
|
||||
register "cio2_prt[0]" = "1"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref gspi0 on
|
||||
chip drivers/nxp/uwb
|
||||
register "name" = ""UWB0""
|
||||
register "desc" = ""NXP UWB Module""
|
||||
register "speed" = "1000000"
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_HIGH(GPP_F21)"
|
||||
register "ce_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A12)"
|
||||
register "ri_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A7)"
|
||||
device spi 0 on end
|
||||
end
|
||||
end
|
||||
device ref gspi1 on
|
||||
chip drivers/spi/acpi
|
||||
register "name" = ""CRFP""
|
||||
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
register "uid" = "1"
|
||||
register "compat_string" = ""google,cros-ec-spi""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
|
||||
register "wake" = "GPE0_DW2_15"
|
||||
device spi 0 on end
|
||||
end # FPMCU
|
||||
end
|
||||
device ref pch_espi on
|
||||
chip ec/google/chromeec
|
||||
# Replicate Brya, except we have 2 ports instead of 3.
|
||||
use conn0 as mux_conn[0]
|
||||
use conn1 as mux_conn[1]
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device ref pmc hidden
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
# C0: Left side (on DB)
|
||||
use usb2_port1 as usb2_port
|
||||
use tcss_usb3_port3 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
# C1: Right side (on MLB)
|
||||
use usb2_port2 as usb2_port
|
||||
use tcss_usb3_port2 as usb3_port
|
||||
device generic 1 alias conn1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0 (DB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
# USB C0 is on the LEFT panel, LEFT side (i.e. rear)
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref tcss_usb3_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C1 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
# USB C1 is on the RIGHT panel, RIGHT side (i.e. rear)
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref tcss_usb3_port2 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0 (DB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
# USB C0 is on the LEFT panel, LEFT side (i.e. rear)
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C1 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
# USB C1 is on the RIGHT panel, RIGHT side (i.e. rear)
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref usb2_port2 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
Loading…
Reference in New Issue